Scientific Programming / 2019 / Article / Tab 4

Research Article

First Steps in Porting the LFRic Weather and Climate Model to the FPGAs of the EuroExa Architecture

Table 4

Performance in Gflop/s using different numbers of matrix-vector IP blocks of Design 1 (full) and Design 2 (reduced) for single and double precision on the UltraScale+ FPGA at different clock frequencies.

Number of matrix-vector IP blocksDesign 2 (reduced interconnect)Design 1 (full interconnect)
Single precisionDouble precisionDouble precision
333 MHz333 MHz250 MHz100 MHz333 MHz250 MHz100 MHz

1515.7510.6386.3157.9483.1362.0148.3
21025.51016.2768.7312.7950.7720.7292.6
31512.01496.41140.2463.91385.91048.5432.7
42008.81995.71508.6616.81808.41370.5562.0
52511.32477.71889.8772.92253.31711.1705.3
62947.12900.22208.0907.02645.92007.9828.2
73414.73351.62545.81047.33033.72314.7960.4
83956.53862.62944.91209.23508.42666.11105.4
94390.04286.33275.11351.7
104761.84629.63527.91465.6
115274.25040.33875.91610.0
125580.15338.84084.61707.9

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