Scientific Programming / 2019 / Article / Tab 6

Research Article

First Steps in Porting the LFRic Weather and Climate Model to the FPGAs of the EuroExa Architecture

Table 6

Maximum clock frequency at which Design 2 still operates correctly for different numbers of matrix-vector blocks.

Number of matrix-vector blocksMaximum clock frequency (MHz)Matrix-vector performance (Gflop/s)

14500.688
44002.372
83333.863
123335.339

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