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The Scientific World Journal
Volume 2013 (2013), Article ID 250802, 10 pages
http://dx.doi.org/10.1155/2013/250802
Research Article

Design of Efficient Full Adder in Quantum-Dot Cellular Automata

1Department of Computer Science and Engineering, National Institute of Technology, Durgapur, India
2Department of Computer Science and Technology, Bengal Engineering and Science University, Shibpur, India

Received 27 March 2013; Accepted 17 May 2013

Academic Editors: X. Ke, H. Pan, and T. Zhou

Copyright © 2013 Bibhash Sen et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Abstract

Further downscaling of CMOS technology becomes challenging as it faces limitation of feature size reduction. Quantum-dot cellular automata (QCA), a potential alternative to CMOS, promises efficient digital design at nanoscale. Investigations on the reduction of QCA primitives (majority gates and inverters) for various adders are limited, and very few designs exist for reference. As a result, design of adders under QCA framework is gaining its importance in recent research. This work targets developing multi-layered full adder architecture in QCA framework based on five-input majority gate proposed here. A minimum clock zone (2 clock) with high compaction (0.01 μm2) for a full adder around QCA is achieved. Further, the usefulness of such design is established with the synthesis of high-level logic. Experimental results illustrate the significant improvements in design level in terms of circuit area, cell count, and clock compared to that of conventional design approaches.