Parallel PWMs Based Fully Digital Transmitter with Wide Carrier Frequency Range

Abstract

The carrier-frequency (CF) and intermediate-frequency (IF) pulse-width modulators (PWMs) based on delay lines are proposed, where baseband signals are conveyed by both positions and pulse widths or densities of the carrier clock. By combining IF-PWM and precorrected CF-PWM, a fully digital transmitter with unit-delay autocalibration is implemented in 180?nm CMOS for high reconfiguration. The proposed architecture achieves wide CF range of 2?M–1?GHz, high power efficiency of 70%, and low error vector magnitude (EVM) of 3%, with spectrum purity of 20?dB optimized in comparison to the existing designs.

1. Introduction

Wireless communication is becoming more and more important and ubiquitous in modern society. To support numbers of communication standards in small and same handheld devices, there are growing demands for flexible transmitters and receivers supporting multimode communications with high efficiency. Recently, lots of researches have been conducted in RF reconfigurable transceivers using novel hardware implementation. This paper focuses on fully digital wireless transmitters.

The existing design [1, 2], employing all-digital phase-locked loop (ADPLL) and delta-sigma modulator, introduces large fractional spurs and requires strict energy match between power branches. The existing transmitters with quadrature [3, 4] or delay-line [5, 6] based intermediate-frequency (IF) pulse-width modulation (PWM), are not apt for low carrier-frequency (CF) applications, under which the band-pass filter (BPF) fails to suppress IF component or harmonics closer to the carrier. The existing radio-frequency (RF) PWM [7] or direct digital frequency synthesizer (DDFS) [8] based transmitters, aiming for low CF conditions, are not considered as fully digital designs, since analogue feedback or mixed-signal configurations are used. The existing architecture [9] employing outphasing amplification technique is not widely used in commerce due to strict matching requirements between dual paths and distortion and efficiency degradation caused by RF power combiner.

In this paper, delay-line based CF-PWM with precorrection logic is proposed, where the only carrier clock is employed to ensure spectrum purity under low CF conditions. By combining IF-PWM for high CF and precorrected CF-PWM for low CF, a fully digital transmitter is presented with wide CF range and high efficiency. A unit-delay autocalibration loop for delay lines is also proposed with reconfigurable carrier frequency 𝑓_𝐶.

2. Architecture

Figure 1 shows the proposed fully digital transmitter with parallel IF- and CF-PWMs. The coordinate rotation digital computer (CORDIC) algorithm accomplishes the conversion from 𝐼/𝑄 to polar coordinate 𝐴/Φ [10]. The wide CF range of 2?M–1?GHz is divided into low 𝑓_𝐶 band of 2?M–100?MHz and high 𝑓_𝐶 band of 80?M–1?GHz. About 20?MHz frequency overlap area is chosen to avoid the switching jitter between high and low 𝑓_𝐶 bands. Under low CF band, the transmitter working in mode “1” and CF-PWM enabling, multibit phase component Φ is mapped to 1/4-period position of the carrier clock, and multibit envelope component 𝐴 is converted to precorrected pulse width of the carrier clock. For high CF case, mode “2” and IF-PWM enabling, phase Φ is conveyed by rising-edge position of the carrier clock, and envelope 𝐴 is represented by pulse width of an IF clock and subsequently converted to pulse density of the carrier clock. The position- and pulse-modulated carrier clock, amplified by a switched-mode class-D power amplifier (PA), is reshaped to the phase- and envelope-modulated sinusoidal carrier by an BPF with CF or IF harmonics suppressed.

Figure 1 

Proposed fully digital transmitter with parallel IF- and CF-PWMs.

The output sinusoidal amplitude 𝑦 and input duty cycle 𝑑 of the BPF conform to (1), according to Fourier series expansion of periodic square wave [7]. For IF-PWM mode, it is the pulse densities rather than pulse widths of the carrier clock that represent baseband envelopes; the BPF handling standard square waves with a fixed duty cycle of 0.5 does not encounter any nonlinear distortion. However, for CF-PWM one, the pulse widths or duty cycles on behalf of baseband envelopes are variable. That is, the BPF not only introduces envelope distortions, but also degrades original rising-edge phases hidden in the modulated carrier due to zero-crossing point deviations. Therefore, to ensure the modulation linearity of CF-PWM mode, an envelope precorrection module with an inverse function of (1) is added to compensate for the envelope offset, and 1/4-period (90°-shifted point) positions rather than rising-edge (zero-crossing point) positions of the carrier clock are modulated to convey phase components without distortion as follows: 2𝑦=𝜋(),2,IF-PWM𝑑=0.5𝜋sin(𝜋×𝑑),CF-PWM. (1)

For CF-PWM mode, only CF clock is involved in signal modulations, whereas IF clock or aliasing is avoided and carrier harmonics are effectively eliminated by BPF. Under IF-PWM condition with less limitation or enough margin between 𝑓_𝐶 and signal bandwidth, although IF clock 𝑓_IF is introduced, the BPF could still suppress IF interferences by setting reasonable relations between 𝑓_𝐶, 𝑓_IF, and BPF bandwidth 𝐵_RF, following (2) 𝑓_𝐶𝐵_RF𝑓≤50,^IF𝐵_RF𝑓≥2.5,𝑘+1>^𝐶𝑓_IF≠𝑘+0.5>𝑘,𝑘=10∼19. (2)

With 6th order BPF, IF spurs lower than -80?dB are ensured when 𝑓_IF is more than 5 times farther than the BPF corner and when the tenth-order or higher IF harmonics with less power locate around the carrier band. With normalized envelope values higher than 0.1, there is at least one whole carrier clock transmitted to convey baseband components during each IF period. In addition, the ratio 𝑓_𝐶/𝑓_IF should not be a multiple of 0.5 to avoid IF harmonics located at 2𝑓_𝐶 down-converts with the carrier at??𝑓_𝐶 into the signal band. Here, 𝑓_IF=𝑓_𝐶/15.4.

3. Implementation

3.1. IF-PWM Mode

Figure 2 shows delay-line based IF-PWM mode for the proposed transmitter. Multibit phase components are mapped to the rising-edge positions of the carrier clock with a fixed duty cycle of 0.5 by employing an 𝑁-level quantizer and an 𝑁-stage delay line where the continuous phases of 0–360° are equidistantly quantized to 𝑁 discrete values. Multibit envelope components are converted to the pulse widths of the IF clock, which are subsequently converted by AND operation to the pulse densities of the carrier clock with the fixed pulse width inversely proportional to 𝑓_𝐶. Under enough margins and perfect values between 𝑓_𝐶, 𝑓_IF, and 𝐵_RF, the BPF effectively suppresses the IF spurs or harmonics. Modulation linearity strongly depends on the quantization resolutions or levels.

Figure 2 

Delay-line based IF-PWM mode for proposed fully digital transmitter.

The function diagram of the IF-PWM mode is shown in Figure 3. For a certain carrier frequency 𝑓_𝐶, the 𝑁-stage delay line with a unit delay of 1/(𝑁×𝑓_𝐶) converts the quantized phase 𝑋 to the rising-edge lag?Φ of the carrier clock. The 𝐿-stage delay line with a unit delay of 1/(2𝐿×𝑓_IF) maps the quantized envelope 𝑌 into the rising-edge lag?Φ of the IF clock. The pulse-width env generated by Φ shapes the pulse density of the carrier clock to represent the envelope component, and the rising-edge lag?Φ of the carrier clock reflects the phase component, respectively.

Figure 3 

Function diagram of IF-PWM architecture.

Assuming baseband envelope 𝐴(𝑡), phase Φ(𝑡), and envelope normalized value 𝐴_std, the modulated carrier clock 𝑐(𝑡) is shown in (3), where square() is the function of periodic square wave and 𝜔_𝐶 is the carrier angular frequency. One has 𝑐(𝑡)=𝐴(𝑡)𝐴_std×square𝜔_𝑐𝑡+Φ(𝑡). (3) After filtered smoothly by the sequent BPF, the modulated sinusoidal carrier 𝑦(𝑡) is shown in (4). Continuous baseband envelope 𝐴 and phase Φ are transmitted: 𝑦(𝑡)=𝐴(𝑡)𝐴_std×2𝜋×sin𝜔_𝑐(𝑡=2𝑡+Φ)𝜋×𝐴_std𝐴(𝑡)×sin𝜔_𝑐𝑡+Φ(𝑡). (4)

3.2. Proposed CF-PWM Mode

Figure 4 shows the proposed delay-line based CF-PWM mode for fully digital transmitter. Multibit phase components are mapped to the rising-edge positions of the carrier clock with a fixed duty cycle of 0.5 by employing an 𝑁-level quantizer and an 𝑁-stage delay line. Multibit envelope components are converted to the pulse widths of the position-modulated carrier clock through the delay differences between the 𝑀- and 2𝑀-stage delay lines and subsequent logic operations. Unlike IF-PWM mode, it is pulse widths rather than densities of the carrier clock that represent baseband envelopes. For ensuring the modulation linearity, both envelope precorrection module with antitrigonometric function and 90° phase-shifted operation are added to compensate for the distortions caused by the BPF with variable pulse-width inputs, as discussed above.

Figure 4 

Proposed delay-line based CF-PWM mode for fully digital transmitter.

The function diagram of the proposed CF-PWM architecture is shown in Figure 5. For a certain carrier clock, the 𝑁-stage delay line with a unit delay of 1/(𝑁×𝑓_𝐶) converts the quantized phase 𝑋 to the rising-edge lag of the carrier clock. The 𝑀- and 2𝑀-stage delay lines with a unit delay of 1/(4𝑀×𝑓_𝐶) subsequently map the precorrected quantization envelope 𝑌 into two different rising-edge lags Φ₁ and Φ₂ on the symmetry of 90° phase-shifted points. The pulse-width env generated by Φ_1-2 represents the precorrected envelope component, and the lag?Φ of the 90° phase-shifted points reflects the phase component, respectively. That is, both pulse-widths and 1/4-period positions of the carrier clock convey baseband signals. Similarly, quantization resolutions or levels determine linearity. The modulated carrier clock 𝑐(𝑡) is shown in the following equation: 𝑐(𝑡)𝑌=0.5×𝑀×square𝜔_𝑐𝑡−90^∘(𝑡2+Φ)=0.5×𝜋𝜋arcsin2×𝐴(𝑡)𝐴_std×square𝜔_𝑐𝑡−90^∘+Φ(𝑡). (5) The modulated sinusoidal carrier 𝑦(𝑡) is shown in (6). Continuous baseband envelope 𝐴 and phase Φ are transmitted. Consider 𝑦(𝑡)=2𝜋2×sin𝜋×0.5×𝜋𝜋arcsin2×𝐴(𝑡)𝐴_std×sin𝜔_𝑐𝑡−90^∘(𝑡)=1+Φ𝐴_std𝐴(𝑡)×sin𝜔_𝑐𝑡−90^∘+Φ(𝑡). (6)

Figure 5 

Function diagram of proposed CF-PWM architecture.

The minimum pulse width 𝑝_min of the modulated carrier clock, shown in (7), is determined by the maximum CF 𝑓_𝐶,max and the minimum normalized envelope 𝐴_std,min. The pulse width resolution Δ𝑝, shown in (8), depends on 𝑓_𝐶 and envelope quantization level 𝑀 and needs to be recognized by the sequent PA. Clearly, the ability of the PA conducting narrow pulses is a critical parameter for the proposed implementation. With finite signal rise and fall time, ultra narrow pulses going through the class-D PA are prone to be trapezoidal or triangular rather than being square, considering the limited working frequency or conducting capability of the present PA. That is why the proposed CF-PWM architecture only aims for low CF range of 2?M–100?MHz. Consider the following equations: 𝑝_min=0.5𝑓_𝐶,max𝐴_std,min,Δ𝑝=0.5𝑀×𝑓_𝐶. (7)(8)

3.3. Unit-Delay Autocalibration

To ensure modulation performances, the unit delay of delay lines needs to be accurate. To meet wide 𝑓_𝐶 range, the unit delay also needs to be reconfigurable. In addition to D flip-flops apt for large unit delay, in most cases the unit delay is small and is implemented by inverters without or with resistive interpolation [5, 11]. However, inverters require accurate delay calibration for high robustness over process and temperature variations. Figure 6 shows the proposed unit-delay calibration loop with wide and reconfigurable𝑓_𝐶.

Figure 6 

Proposed unit-delay autocalibration loop with reconfigurable 𝑓𝐶.

The phase difference between the periodic clock input and 90°-shifted clock corresponding to 𝐾 unit delays is measured and converted to an error voltage by an XOR gate followed by a low-pass filter (LPF) and a sequent comparator. The error voltage sent to an integrator with driver buffer is accumulated and fed to the power supply 𝑉_DD of delay cells, which inversely modifies the unit delay. Under the negative feedback operation with closed-loop 𝑉_DD calibration, for a certain clock 𝑓_in (𝑓_𝐶 or 𝑓_IF), the unit delays of open-loop delay lines are accurately achieved by strict match designs and conform to (9), respectively, for different delay lines of the phase path and IF- and CF-PWMs. By setting matched inverter number in each delay cell and perfect 𝑉_DD range of delay cells, reconfigurable??𝑓_𝐶 and corresponding unit delays are accomplished as follows: 𝜏=0.25𝐾×𝑓_in=1𝑁×𝑓_𝐶𝑁,Phase-Path𝐾=4,𝑓_in=𝑓_𝐶,12𝐿×𝑓_IF𝐿,IF-PWM𝐾=2,𝑓_in=𝑓_IF,14𝑀×𝑓_𝐶,CF-PWM𝐾=𝑀,𝑓_in=𝑓_𝐶. (9)

4. Experimental Results

The proposed fully digital transmitter is designed in 180?nm CMOS with external class-D PA and BPF. Excluding the PA, the proposed implementation only dissipates ultra low power of 100?µW from 1.8?V power supply. The transmitter achieves a power efficiency of 70%, according to circuit-level simulations. The quantization levels are 256 and 128 for the phase and envelope paths, respectively.

The supply voltage of delay cells can be changed from 1.4 to 2.2?V, which corresponds to the minimum unit delays of 7.8–3.9?ps for the phase path, 120.3–60.1?ps for the IF-PWM, and 39.0–19.5?ps for the CF-PWM, according to circuit-level simulations of three groups of different delay lines in the nominal case. As a result, the CF ranges of 50–100?MHz for the CF-PWM mode and 0.5–1?GHz for the IF-PWM one are gotten. By adding matched inverters in each group of delay cells, the lower CF range is also covered and the wide CF range of 2?M–1?GHz is achieved. For a certain baseband signal with normalized envelope range of 0.15–1.0, with 𝑓_𝐶 less than 100?MHz, the 𝑝_min and Δ𝑝 of the CF-PWM mode are 0.75?ns and 0.04?ns, respectively, which could be recognized by the present PA.

Figure 7 shows the simulated transmitter components conveyed by the proposed architecture with comparison to the baseband ones for 8PSK signal with an envelope range of 0.22~1.45?V. The proposed transmitter conveys the baseband components very well with the simulated error vector magnitude (EVM) of 3%. Little distortions result from limited quantization resolutions and slight PA push-pull asymmetry. An ideal receiver reconstructing the transmitted components is implemented in Matlab.

(a)

(b)

(c)

(d)

Figure 7 

Simulated transmitter components conveyed by proposed architecture with comparison to baseband ones.

Figure 8 shows the simulated transmitter normalized far and near spectrums centered at 50?MHz for CF-PWM mode and at 200?MHz for IF-PWM one. The roll-off feature of spectrum side lobes is determined by the baseband shaping filter. The noise floor less than 60?dB is observed below the carrier, and 20?dB spectrum optimization is achieved when compared to the existing designs [4, 5] with the noise floor at 40?dB below the carrier. For CF-PWM mode, no any other frequency components including spurs and harmonics exist, except for the carrier. For IF-PWM mode, IF spurs located at even multiples of 𝑓_IF from 𝑓_𝐶 are observed and less than -80?dB. Hence, the proposed transmitter achieves high spectrum purity.

(a)

(b)

Figure 8 

Simulated transmitter normalized far and near spectrums: (a) CF-PWM centered at 50 MHz; and (b) IF-PWM centered at 200 MHz.

5. Conclusions

By combining delay-line based IF-PWM for high 𝑓_𝐶 band and proposed CF-PWM with precorrection for low 𝑓_𝐶 band, a fully digital transmitter is implemented in 180?nm CMOS, with wide CF range of 2?M–1?GHz and high power efficiency of 70%. A unit-delay autocalibration circuit with closed-loop detection and open-loop adjustment is presented to support 𝑓_𝐶 reconfiguration. The experimental results show that the proposed architecture transmits baseband components well with high spectrum purity and low EVM of 3%. Compared to the existing designs, 20?dB spectrum optimization is achieved. Chip prototype will be considered as a future work to further verify the proposed transmitter architecture.

Acknowledgments

The authors would like to thank the National Natural Science Foundation of China (no. 61306037 and no. 61201182) for the financial support.