Table of Contents Author Guidelines Submit a Manuscript
The Scientific World Journal
Volume 2014 (2014), Article ID 102651, 11 pages
http://dx.doi.org/10.1155/2014/102651
Research Article

Application of Butterfly Clos-Network in Network-on-Chip

1Jiangxi University of Science and Technology, Ganzhou 341000, China
2School of Information Science and Engineering, Jishou University, Jishou 416000, China

Received 28 August 2013; Accepted 17 November 2013; Published 29 January 2014

Academic Editors: Y. Lu and F. Yu

Copyright © 2014 Hui Liu et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Linked References

  1. L. Benini and G. de Micheli, “Networks on chips: a new SoC paradigm,” Computer, vol. 35, no. 1, pp. 70–78, 2002. View at Publisher · View at Google Scholar · View at Scopus
  2. D. Zhao and Y. Wang, “SD-MAC: design and synthesis of a hardware-efficient collision-free QoS-aware MAC protocol for wireless network-on-chip,” IEEE Transactions on Computers, vol. 57, no. 9, pp. 1230–1245, 2008. View at Publisher · View at Google Scholar · View at Scopus
  3. A. Hemani, S. Kumar, A. Postula, J. Oberg, M. Millberg, and D. Lindqvist, “An architecture for billion transistor era,” in Proceeding of the IEEE Nor-Chip Conference, 2000.
  4. P. Guerrier and A. Grenier, “A generic architecture for on-chip packet-switched interconnections,” in Proceedings of the Design, Automation and Test in Europe Conference and Exhibition (DATE '00), pp. 250–2256, Paris, France, 2000. View at Publisher · View at Google Scholar
  5. B. Akesson, Predictable and composable system-on-chip memory controllers. [Ph.D. thesis], Department of Electrical Engineering, Eindhoven University of Technology, 2010.
  6. B. Akesson, K. Goossens, and M. Ringhofer, “Predator: a predictable SDRAM memory controller,” in Proceedings of the 5th International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS '07), pp. 251–256, IEEE Computer Society, Salzburg, Austria, October 2007. View at Publisher · View at Google Scholar · View at Scopus
  7. Intel Atom Processor, 2008.
  8. R. Kalla, B. Sinharoy, and J. M. Tendler, “IBM Power5 chip: a dual-core multithreaded processor,” IEEE Micro, vol. 24, no. 2, pp. 40–47, 2004. View at Publisher · View at Google Scholar · View at Scopus
  9. K. Kevin, “Best servers of 2004: where multicore is the norm,” MicroProcessor Report, 2005. View at Google Scholar
  10. P. Kongetira, K. Aingaran, and K. Olukotun, “Niagara: a 32-way multithreaded sparc processor,” IEEE Micro, vol. 25, no. 2, pp. 21–29, 2005. View at Publisher · View at Google Scholar · View at Scopus
  11. T. A. Bartic, J.-Y. Mignolet, V. Nollet et al., “Highly scalable network on chip for reconfigurable systems,” in Proceedings of the 5th International Symposium on System-on-Chip (SoC '03), pp. 79–82, November 2003. View at Scopus
  12. C. Wang, W.-H. Hu, and N. Bagherzadeh, “A wireless network-on-chip design for multicore platforms,” in Proceedings of the 19th International Euromicro Conference on Parallel, Distributed, and Network-Based Processing (PDP '11), pp. 409–416, February 2011. View at Publisher · View at Google Scholar · View at Scopus
  13. M. Nickray, M. Dehyadgari, and A. Afzali-kusha, “Power and delay optimization for network on chip,” in Proceedings of the European Conference on Circuit Theory and Design (ECCTD '05), vol. 3, pp. 273–276, September 2005. View at Publisher · View at Google Scholar · View at Scopus
  14. T. Simunic, S. P. Boyd, and P. Glynn, “Managing power consumption in networks on chips,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 12, no. 1, pp. 96–107, 2004. View at Publisher · View at Google Scholar · View at Scopus
  15. N. Banerjee, P. Vellanki, and K. S. Chatha, “A power and performance model for network-on-chip architectures,” in Proceedings of the Design, Automation and Test in Europe Conference and Exhibition (DATE '04), vol. 2, pp. 1250–1255, February 2004. View at Publisher · View at Google Scholar · View at Scopus
  16. J. Kim, D. Park, T. Theocharides, N. Vijaykrishnan, and C. R. Das, “A low latency router supporting adaptivity for on-chip interconnects,” in Proceedings of the 42nd Design Automation Conference (DAC '05), pp. 559–564, June 2005. View at Scopus
  17. E. Rijpkema, K. G. W. Goossens, A. Radulescu et al., “Trade offs in the design of a router with both guaranteed and best-effort services for networks on chip,” in Proceedings of the Design, Automation and Test in Europe Conference and Exhibition (DATE '03), 2003.
  18. A. Portero, R. Pla, and J. Carrabina, “SystemC implementation of a NoC,” in Proceedings of the IEEE International Conference on Industrial Technology (ICIT '05), pp. 1132–1135, December 2005. View at Publisher · View at Google Scholar · View at Scopus
  19. K. Stewart and S. Tragoudas, “Interconnect testing for networks on chips,” in Proceedings of the 24th IEEE VLSI Test Symposium (VTS '06), pp. 100–105, May 2006. View at Publisher · View at Google Scholar · View at Scopus
  20. S. Scott, D. Abts, J. Kim, and W. J. Dally, “The BlackWidow high-radix clos network,” in Proceedings of the 33rd International Symposium on Computer Architecture (ISCA '06), pp. 16–27, June 2006. View at Publisher · View at Google Scholar · View at Scopus
  21. T. Morimura, K. Iwai, and H. Amano, “Hierarchical multistage interconnection network R-Clos,” Electronics and Communications in Japan III, vol. 89, no. 11, pp. 30–39, 2006. View at Publisher · View at Google Scholar · View at Scopus
  22. H. Y. Lee, F. K. Hwang, and J. D. Carpinelli, “A new decomposition algorithm for rearrangeable clos interconnection networks,” IEEE Transactions on Communications, vol. 44, no. 11, pp. 1572–1578, 1996. View at Publisher · View at Google Scholar · View at Scopus
  23. J. Kim, C. Kiyoung, and G. Loh, “Exploiting new Interconnect technologies in on-chip communication,” IEEE Journal on Emerging and Selected Topics in Circuits and Systems, vol. 2, no. 2, pp. 124–136, 2012. View at Publisher · View at Google Scholar
  24. J. Kim, J. Balfour, and W. J. Dally, “Flattened butterfly topology for on-chip networks,” in Proceedings of the 40th IEEE/ACM International Symposium on Microarchitecture (MICRO '07), pp. 172–182, IEEE Computer Society. MICRO, Chicago, Ill, USA, December 2007. View at Publisher · View at Google Scholar · View at Scopus
  25. S. Lin, J. Shi, and H. Chen, “Designing cost-effective network-on-chip by dual-channel access mechanism,” Journal of Systems Engineering and Electronics, vol. 22, no. 4, pp. 557–564, 2011. View at Publisher · View at Google Scholar · View at Scopus
  26. K. Salah and K. El-Badawi, “On modelling and analysis of receive livelock and CPU utilization in high-speed networks,” International Journal of Computers and Applications, vol. 28, no. 2, pp. 162–169, 2006. View at Google Scholar · View at Scopus
  27. C. Martínez, E. Vallejo, R. Beivide, C. Izu, and M. Moretó, “Dense Gaussian networks: suitable topologies for on-chip multiprocessors,” International Journal of Parallel Programming, vol. 34, no. 3, pp. 193–211, 2006. View at Publisher · View at Google Scholar · View at Scopus
  28. S. Deb, A. Ganguly, P. P. Pande, B. Belzer, and D. Heo, “Wireless NoC as interconnection backbone for multicore chips: promises and challenges,” IEEE Journal on Emerging and Selected Topics in Circuits and Systems, vol. 2, no. 2, pp. 228–239, 2012. View at Publisher · View at Google Scholar