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The Scientific World Journal
Volume 2014, Article ID 131568, 9 pages
http://dx.doi.org/10.1155/2014/131568
Research Article

Hardware Implementation of 32-Bit High-Speed Direct Digital Frequency Synthesizer

1Department of Electronics, College of Engineering, Diyala University, Baqubah, Diyala 32001, Iraq
2Department of Electrical, Electronics & System Engineering, Faculty of Engineering, Universiti Kebangsaan Malaysia (UKM), 43600 Bangi, Malaysia
3Institute of Microengineering and Nanoelectronics (IMEN), Universiti Kebangsaan Malaysia (UKM), 43600 Bangi, Malaysia

Received 4 February 2014; Revised 13 March 2014; Accepted 29 April 2014; Published 2 June 2014

Academic Editor: Robert Adams

Copyright © 2014 Salah Hasan Ibrahim et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Abstract

The design and implementation of a high-speed direct digital frequency synthesizer are presented. A modified Brent-Kung parallel adder is combined with pipelining technique to improve the speed of the system. A gated clock technique is proposed to reduce the number of registers in the phase accumulator design. The quarter wave symmetry technique is used to store only one quarter of the sine wave. The ROM lookup table (LUT) is partitioned into three 4-bit sub-ROMs based on angular decomposition technique and trigonometric identity. Exploiting the advantages of sine-cosine symmetrical attributes together with XOR logic gates, one sub-ROM block can be removed from the design. These techniques, compressed the ROM into 368 bits. The ROM compressed ratio is 534.2 : 1, with only two adders, two multipliers, and XOR-gates with high frequency resolution of 0.029 Hz. These techniques make the direct digital frequency synthesizer an attractive candidate for wireless communication applications.