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The Scientific World Journal
Volume 2014, Article ID 241214, 7 pages
http://dx.doi.org/10.1155/2014/241214
Research Article

Theoretical Analysis and Characterization of Multi-Islands Single-Electron Devices with Applications

Faculty of Sciences, Laboratory of Microelectronics and Instrumentation, 5019 Monastir, Tunisia

Received 31 August 2013; Accepted 23 October 2013; Published 5 February 2014

Academic Editors: P. Li and E. Poirier

Copyright © 2014 Amine Touati et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Linked References

  1. International Technology Roadmap for Semiconductors (ITRS), 2012, http://www.nist.gov/pml/div683/conference/upload/Diebold_final.pdf.
  2. D. V. Averin and K. K. Likharev, Mesoscopic Phenomena in Solids, Elsevier, Amsterdam, 1991.
  3. A. Touati, S. Chatbouri, N. Sghaier, and A. Kalboussi, “New model for drain and gate current of single-electron transistor at high temperature,” World Journal of Nano Science and Engineering, vol. 2, pp. 171–175, 2012. View at Google Scholar
  4. K. Ohkura, T. Kitade, and A. Nakajima, “Periodic Coulomb oscillations in Si single-electron transistor based on multiple islands,” Journal of Applied Physics, vol. 98, no. 12, Article ID 124503, 2005. View at Publisher · View at Google Scholar · View at Scopus
  5. W. Chen and H. Ahmed, “Metal-based single electron transistors,” Journal of Vacuum Science and Technology B, vol. 15, no. 4, pp. 1402–1405, 1997. View at Google Scholar · View at Scopus
  6. A. Touati, S. Chatbouri, N. Sghaier, and A. Kalboussi, “Study of two one-dimensional multi tunnel junctions arrays structures by SIMON,” World Journal of Nano Science and Engineering, vol. 2, pp. 176–180, 2012. View at Google Scholar
  7. I. Kim, S. Han, H. Kim et al., “Room temperature single electron effects in si quantum dot memory with oxide-nitride tunneling dielectrics,” in Proceedings of the IEEE International Electron Devices Meeting, pp. 111–114, December 1998. View at Scopus
  8. Z. Liu, C. Lee, V. Narayanan, G. Pei, and E. C. Kan, “Metal nanocrystal memories—part II: electrical characteristics,” IEEE Transactions on Electron Devices, vol. 49, no. 9, pp. 1614–1622, 2002. View at Publisher · View at Google Scholar · View at Scopus
  9. S. Tang, C. Mao, Y. Liu, D. Q. Kelly, and S. K. Banerjee, “Nanocrystal flash memory fabricated with protein-mediated assembly,” in Proceedings of the IEEE International Electron Devices Meeting (IEDM '05), pp. 174–177, December 2005. View at Publisher · View at Google Scholar · View at Scopus
  10. F. Rana, S. Tiwari, and J. J. Welser, “Kinetic modelling of electron tunneling processes in quantum dots coupled to field-effect transistors,” Superlattices and Microstructures, vol. 23, no. 3-4, pp. 757–770, 1998. View at Google Scholar · View at Scopus
  11. C. Wasshuber, H. Kosina, and S. Selberherr, “SIMON: a simulator for single-electron tunnel devices and circuits,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 16, no. 9, pp. 937–944, 1997. View at Publisher · View at Google Scholar · View at Scopus
  12. C. Wasshuber, Computational Single-Electronic, Springer, Vienna, Austria, 2001.
  13. G. Y. Hu and R. F. O'Connell, “Exact solution for the charge soliton in a one-dimensional array of small tunnel junctions,” Physical Review B, vol. 49, no. 23, pp. 16773–16776, 1994. View at Publisher · View at Google Scholar · View at Scopus
  14. A. Fazio, “Future directions of non-volatile memory in compute applications,” in Proceedings of the International Electron Devices Meeting (IEDM '09), pp. 1–4, December 2009. View at Publisher · View at Google Scholar · View at Scopus
  15. H. Tanaka, M. Kido, K. Yahashi et al., “Bit Cost Scalable technology with and plug process for ultra high density flash memory,” in Proceedings of the Symposium on VLSI Technology (VLSIT '07), pp. 14–15, June 2007. View at Publisher · View at Google Scholar · View at Scopus
  16. A. Hubert, E. Nowak, K. Tachi et al., “A stacked SONOS technology, up to 4 levels and 6nm crystalline nanowires, with gate-all-around or independent gates (φ-Flash), suitable for full 3D integration,” in Proceedings of the International Electron Devices Meeting (IEDM '09), pp. 1–4, December 2009. View at Publisher · View at Google Scholar · View at Scopus
  17. K.-T. Park, M. Kang, S. Hwang et al., “A fully performance compatible 45 nm 4-gigabit three dimensional double-stacked multi-level NAND flash memory with shared bit-line structure,” IEEE Journal of Solid-State Circuits, vol. 44, no. 1, pp. 208–216, 2009. View at Publisher · View at Google Scholar · View at Scopus
  18. E.-K. Lai, H.-T. Lue, Y.-H. Hsiao et al., “A highly stackable Thin-Film Transistor (TFT) NAND-type flash memory,” in Proceedings of the Symposium on VLSI Technology (VLSIT '06), pp. 46–47, June 2006. View at Scopus
  19. J.-C. Wang, C.-T. Lin, and C.-H. Chen, “Gadolinium oxide nanocrystal nonvolatile memory with HfO2/Al2O3 nanostructure tunneling layers,” Nanoscale Research Letters, vol. 7, article 177, 2012. View at Publisher · View at Google Scholar · View at Scopus
  20. C. Lee, J. Meteer, V. Narayanan, and E. C. Kan, “Self-assembly of metal nanocrystals on ultrathin oxide for nonvolatile memory applications,” Journal of Electronic Materials, vol. 34, no. 1, pp. 1–11, 2005. View at Google Scholar · View at Scopus
  21. K. Uchida, J. Koga, R. Ohba, S.-I. Takagi, and A. Toriumi, “Silicon single-electron tunneling device fabricated in an undulated ultrathin silicon-on-insulator film,” Journal of Applied Physics, vol. 90, no. 7, pp. 3551–3557, 2001. View at Publisher · View at Google Scholar · View at Scopus
  22. A. Touati and A. Kalboussi, “Volatile and non-volatile single electron memory,” Journal of Nano- & Electronic Physics, vol. 5, no. 3, pp. 03003.1–03003.7, 2013. View at Google Scholar
  23. M. H. Devoret, D. Esteve, and C. Urbina, “Single-electron transfer in metallic nanostructures,” Nature, vol. 360, no. 6404, pp. 547–553, 1992. View at Google Scholar · View at Scopus
  24. J. Lambe and R. C. Jaklevic, “Charge-quantization studies using a tunnel capacitor,” Physical Review Letters, vol. 22, no. 25, pp. 1371–1375, 1969. View at Publisher · View at Google Scholar · View at Scopus
  25. A. Nainani, R. O. Y. A, P. K. Singh, G. Mukhopadhyay, and J. Vasi, “Electrostatics and its effect on spatial distribution of tunnel current in metal Nanocrystal flash memories,” in Proceedings of the International Conference on Memory Technology and Devices, 2007.
  26. M. Troudi, N. Sghaier, A. Kalboussi, and A. Souifi, “Concept of new photodetector based on single electron transistor for single charge detection,” EPJ Applied Physics, vol. 46, no. 2, Article ID 20301, 2009. View at Publisher · View at Google Scholar · View at Scopus
  27. S. Chatbouri, A. Touati, M. Troudi, N. Sghaier, and A. Kalboussi, “Multiple tunnel junctions based nanowire photodetector model for single charge detection,” The European Physical Journal: Applied Physics, vol. 63, no. 1, 4 pages, 2013. View at Publisher · View at Google Scholar
  28. C. Soci, A. Zhang, X.-Y. Bao, H. Kim, Y. Lo, and D. Wang, “Nanowire photodetectors,” Journal of Nanoscience and Nanotechnology, vol. 10, no. 3, pp. 1430–1449, 2010. View at Publisher · View at Google Scholar · View at Scopus