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The Scientific World Journal
Volume 2014 (2014), Article ID 286084, 12 pages
http://dx.doi.org/10.1155/2014/286084
Research Article

Characterizing the Effects of Intermittent Faults on a Processor for Dependability Enhancement Strategy

1Multicore Research Institute, High Performance CPU Center, Tsinghua University, Building F.I.T, Beijing 100084, China
2School of Computer Science, Harbin Institute of Technology, No. 155 Fanrong Street, Nangang District, Harbin 150001, China
3School of Computer and Communication Engineering, University of Science and Technology Beijing, No. 30 Xueyuan Road, Haidian District, Beijing 100083, China

Received 31 August 2013; Accepted 17 March 2014; Published 28 April 2014

Academic Editors: J. Shu and F. Yu

Copyright © 2014 Chao(Saul) Wang et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Linked References

  1. “Process integration, devices and structures,” The International Technology Roadmap for Semiconductors, p. 8, Update, 2006.
  2. P. Gil, J. Arlat, H. Madeira et al., “Fault Representativeness,” Deliverable ETIE2. DBench European Project IST-2000-25425.
  3. P. M. Wells, K. Chakraborty, and G. S. Sohi, “Mixed-mode multicore reliability,” in Proceedings of the 14th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS '14), pp. 169–180, March 2009. View at Publisher · View at Google Scholar · View at Scopus
  4. C. Constantinescu, “Impact of intermittent faults on nanocomputing devices,” in Proceedings of the Workshop on Dependable and Secure Nanocomputing (WDSN '07), Edinburgh, UK, 2007.
  5. S. Kim and A. K. Somani, “Soft error sensitivity characterization for microprocessor dependability enhancement strategy,” in Proceedings of the International Conference on Dependable Systems and Networks (DNS '02), pp. 416–425, June 2002. View at Scopus
  6. J. Gracia-Moran, D. Gil-Tomas, L. J. Saiz-Adalid, J. C. Baraza, and P. J. Gil-Vicente, “Experimental validation of a fault tolerant microcomputer system against intermittent faults,” in Proceedings of the IEEE/IFIP International Conference on Dependable Systems and Networks (DSN '10), pp. 413–418, July 2010. View at Publisher · View at Google Scholar · View at Scopus
  7. M.-L. Li, P. Ramachandran, U. R. Karpuzcu, S. K. S. Hari, and S. V. Adve, “Accurate microarchitecture-level fault modeling for studying hardware faults,” in Proceedings of the IEEE International Conference on Mechatronics and Automation (ICMA '08), pp. 105–116, August 2008. View at Publisher · View at Google Scholar · View at Scopus
  8. J. C. Smolens, Fingerprinting: hash-based error detection in microprocessors [CMU doctor thesis], 2008.
  9. D. Gil-Tomás, J. Gracia-Morán, J.-C. Baraza-Calvo et al., “Analyzing the impact of intermittent faults on microprocessors applying fault injection,” IEEE Design and Test of Computers, vol. 29, no. 6, pp. 66–673, 2013. View at Google Scholar
  10. G. P. Saggese, A. Vetteth, Z. Kalbarczyk, and R. Iyer, “Microprocessor sensitivity to failures: control vs. execution and combinational vs. sequential logic,” in Proceedings of the International Conference on Dependable Systems and Networks, pp. 760–769, July 2005. View at Publisher · View at Google Scholar · View at Scopus
  11. J. Carretero, X. Vera, P. Chaparro, and J. Abella, “On-line failure detection in memory order buffers,” in Proceedings of the International Test Conference (ITC '08), October 2008. View at Publisher · View at Google Scholar · View at Scopus
  12. X. Vera, J. Abella, J. Carretero, P. Chaparro, and A. González, “Online error detection and correction of erratic bits in register files,” in Proceedings of the 15th IEEE International On-Line Testing Symposium (IOLTS '09), pp. 81–86, June 2009. View at Publisher · View at Google Scholar · View at Scopus
  13. J. Abella, X. Vera, O. Unsal, O. Ergin, and A. González, “Fuse: a technique to anticipate failures due to degradation in ALUs,” in Proceedings of the 13th IEEE International On-Line Testing Symposium (IOLTS '07), pp. 15–22, July 2007. View at Publisher · View at Google Scholar · View at Scopus
  14. J. Abella, P. Chaparro, X. Vera, J. Carretero, and A. González, “On-line failure detection and confinement in caches,” in Proceedings of the 14th IEEE International On-Line Testing Symposium (IOLTS '08), pp. 3–9, July 2008. View at Publisher · View at Google Scholar · View at Scopus
  15. C. Constantinescu, “Trends and challenges in VLSI circuit reliability,” IEEE Micro, vol. 23, no. 4, pp. 14–19, 2003. View at Publisher · View at Google Scholar · View at Scopus
  16. J. Srinivasan, S. V. Adve, P. Bose, and J. A. Rivers, “The case for lifetime reliability-aware microprocessors,” in Proceedings of the 31st Annual International Symposium on Computer Architecture, pp. 276–287, June 2004. View at Scopus
  17. C. M. Tan and A. Roy, “Electromigration in ULSI interconnects,” Materials Science and Engineering R: Reports, vol. 58, no. 1-2, pp. 1–75, 2007. View at Publisher · View at Google Scholar · View at Scopus
  18. J. Abella, X. Vera, O. S. Unsal, O. Ergin, A. Gonza'lez, and J. W. Tschanz, “Refueling: preventing wire degradation due to electromigration,” IEEE Computer Society, vol. 28, no. 6, pp. 37–46, 2008. View at Google Scholar
  19. R. Degraeve, B. Kaczer, and G. Groeseneken, “Reliability: a possible showstopper for oxide thickness scaling?” Semiconductor Science and Technology, vol. 15, no. 5, pp. 436–444, 2000. View at Publisher · View at Google Scholar · View at Scopus
  20. X. Li, J. Qin, and J. B. Bernstein, “Compact modeling of MOSFET wearout mechanisms for circuit-reliability simulation,” IEEE Transactions on Device and Materials Reliability, vol. 8, no. 1, pp. 98–121, 2008. View at Publisher · View at Google Scholar · View at Scopus
  21. V. Huard, M. Denais, and C. Parthasarathy, “NBTI degradation: from physical mechanisms to modelling,” Microelectronics Reliability, vol. 46, no. 1, pp. 1–23, 2006. View at Publisher · View at Google Scholar · View at Scopus
  22. Failure Mechanisms and Models for Semiconductor Devices, JEDEC Publication JEP122-A, 2002.
  23. A. DeHon, H. M. Quinn, and N. P. Carter, “Vision for cross-layer optimization to address the dual challenges of energy and reliability,” in Proceedings of the Design, Automation and Test in Europe Conference and Exhibition (DATE '10), pp. 1017–1022, March 2010. View at Scopus
  24. C. Constantinescu, “Intermittent faults and effects on reliability of integrated circuits,” in Proceedings of the 54th Annual Reliability and Maintainability Symposium (RAMS '08), January 2008. View at Publisher · View at Google Scholar · View at Scopus
  25. D. Gil, L. J. Saiz, J. Gracia, J. C. Baraza, and P. J. Gil, “Injecting intermittent faults for the dependability validation of commercial microcontrollers,” in Proceedings of the IEEE International High Level Design Validation and Test Workshop (HLDVT '08), pp. 177–184, November 2008. View at Publisher · View at Google Scholar · View at Scopus
  26. L. Rashid, K. Pattabiraman, and S. Gopalakrishnan, “Towards understanding the effects of intermittent hardware faults on programs,” in Proceedings of the International Conference on Dependable Systems and Networks Workshops (DSN-W '10), pp. 101–106, July 2010. View at Publisher · View at Google Scholar · View at Scopus
  27. J. Wei, L. Rashid, K. Pattabiraman, and S. Gopalakrishnan, “Comparing the effects of intermittent and transient hardware faults on programs,” in Proceedings of the IEEE/IFIP 41st International Conference on Dependable Systems and Networks Workshops (DSN-W '11), pp. 53–58, June 2011. View at Publisher · View at Google Scholar · View at Scopus
  28. J. Gracia, L. J. Saiz, J. C. Baraza, D. Gil, and P. J. Gil, “Analysis of the influence of intermittent faults in a microcontroller,” in Proceedings of the IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS '08), pp. 80–85, April 2008. View at Publisher · View at Google Scholar · View at Scopus
  29. S. Pan, Y. Hu, and X. Li, “IVF: characterizing the vulnerability of microprocessor structures to intermittent faults,” in Proceedings of the Design, Automation and Test in Europe Conference and Exhibition (DATE '10), pp. 238–243, March 2010. View at Scopus