A Modified Implementation of Tristate Inverter Based Static Master-Slave Flip-Flop with Improved Power-Delay-Area Product

<table class="table-group" width="800px"><tr class="fig-image" id="a"><td><img alt="453675.fig.005a" src="https://static.hindawi.com/articles/tswj/volume-2014/453675/figures/453675.fig.005a.jpg"/></td></tr><tr class="fig-caption"><td align="center"><table><tr><td><b>(a) </b>mC<sup>2</sup>MOSff1</td></tr></table></td></tr><tr class="fig-image" id="b"><td><img alt="453675.fig.005b" src="https://static.hindawi.com/articles/tswj/volume-2014/453675/figures/453675.fig.005b.jpg"/></td></tr><tr class="fig-caption"><td align="center"><table><tr><td><b>(b) </b>mC<sup>2</sup>MOSff2</td></tr></table></td></tr></table>

<table>Schematic diagrams of the proposed designs.</table>

The Scientific World Journal

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Figure 5

Figure 5: A Modified Implementation of Tristate Inverter Based Static Master-Slave Flip-Flop with Improved Power-Delay-Area Product 