Effects of Gate Stack Structural and Process Defectivity on High- Dielectric Dependence of NBTI Reliability in 32 nm Technology Node PMOSFETs

Figure 12

(a) Threshold voltage shift and (b) time evolution of hole and interface trap densities because of the effect of different dipole surface densities. (c) Hole and interface trap densities in relation to different SiO₂ interface layer thickness for a different dipole layer.

(a)

(b)

(c)