Investigation of a Novel Common Subexpression Elimination Method for Low Power and Area Efficient DCT Architecture

Table 2

12-bit precise DCT coefficient in CSD form and reduction of nonzero bits.

Coefficient	Decimal value	Binary representation	CSD representation	Reduction of Nonzero bits
𝑐1	0.4904	0.011111011000	0.000001010001	4
𝑐2	0.4619	0.011101100100	0.100010100100	2
𝑐3	0.4157	0.011010100110	0.101010101010	0
𝑐4	0.3536	0.010110101000	0.101010101000	0
𝑐5	0.2778	0.010001110001	0.010010010001	1
𝑐6	0.1913	0.001100001111	0.010100010001	2
𝑐7	0.0975	0.000110001111	0.001010010001	2