Investigation of a Novel Common Subexpression Elimination Method for Low Power and Area Efficient DCT Architecture

Table 6

Resource usages and DCT computing cycles of the proposed architecture.

Total number of adders	9
Total number of subtractors	6
Total number of add/sub	7
Total number of fixed shifts	13
Total number of selectors	2
DSP slices	0
Memory modules	0
Total number of clock cycles for computing 1D-DCT	4+8
Total number of clock cycles for computing 8×8 2D-DCT	12+64