Research Article

Investigation of a Novel Common Subexpression Elimination Method for Low Power and Area Efficient DCT Architecture

Table 8

Performance analysis of different 1D-DCT architectures on Xilinx FPGAs.

FPGA chipXC2VP30XC2VP50XC3S200

Architecture[40]Proposed[33]Proposed[40]Proposed
ImplementationDACSD + New-CSECSD + CSECSD + New-CSEDACSD + New-CSE
Precision (bits)9121112912
Number of slices936347454347793340
Operating clock frequency (MHz)9920511912061163.84
Dynamic power dissipation (mW)83.46639354523
Multiport input memory (number of read ports)Yes (8)No (1)Yes (8)No (1)Yes (8)No (1)