Research Article
Investigation of a Novel Common Subexpression Elimination Method for Low Power and Area Efficient DCT Architecture
Table 8
Performance analysis of different 1D-DCT architectures on Xilinx FPGAs.
| FPGA chip | XC2VP30 | XC2VP50 | XC3S200 |
| Architecture | [40] | Proposed | [33] | Proposed | [40] | Proposed | Implementation | DA | CSD + New-CSE | CSD + CSE | CSD + New-CSE | DA | CSD + New-CSE | Precision (bits) | 9 | 12 | 11 | 12 | 9 | 12 | Number of slices | 936 | 347 | 454 | 347 | 793 | 340 | Operating clock frequency (MHz) | 99 | 205 | 119 | 120 | 61 | 163.84 | Dynamic power dissipation (mW) | 83.4 | 66 | 39 | 35 | 45 | 23 | Multiport input memory (number of read ports) | Yes (8) | No (1) | Yes (8) | No (1) | Yes (8) | No (1) |
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