Investigation of a Novel Common Subexpression Elimination Method for Low Power and Area Efficient DCT Architecture

Table 9

Performance analysis of different 1D-DCT architectures on Altera FPGA.

FPGA chip	Cyclone II (EP2C35F672C6)
Architecture	[38]	[26]	Proposed
Implementation	Modified Loeffler	Modified Loeffler	CSD + New-CSE
Precision (bits)	12	12	12
Logic elements	1146	1109	713
Operating clock frequency (MHz)	128.25	139.55	191.79
Dynamic power dissipation (mW)	57	52	42
Multiport input memory (number of read ports)	Yes (8)	Yes (8)	No (1)