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The Scientific World Journal
Volume 2014 (2014), Article ID 982728, 7 pages
http://dx.doi.org/10.1155/2014/982728
Research Article

A Test Data Compression Scheme Based on Irrational Numbers Stored Coding

1School of Computer and Information, Anqing Normal University, Anqing 246011, China
2Department of Science Research, Anqing Normal University, Anqing 246011, China

Received 27 June 2014; Revised 2 August 2014; Accepted 2 August 2014; Published 28 August 2014

Academic Editor: Yunqiang Yin

Copyright © 2014 Hai-feng Wu et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Linked References

  1. L. Li, K. Chakrabarty, S. Kajihara, and S. Swaminathan, “Efficient space/time compression to reduce test data volume and testing time for IP cores,” in Proceedings of the 18th International Conference on VLSI Design, pp. 53–58, January 2005. View at Publisher · View at Google Scholar · View at Scopus
  2. A. Jas, J. Ghosh-Dastidar, M. Ng, and N. A. Touba, “An efficient test vector compression scheme using selective huffman coding,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 22, no. 6, pp. 797–806, 2003. View at Publisher · View at Google Scholar · View at Scopus
  3. M. Tehranipoor, M. Nourani, and K. Chakrabarty, “Nine-coded compression technique for testing embedded cores in SoCs,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 13, no. 6, pp. 719–731, 2005. View at Publisher · View at Google Scholar · View at Scopus
  4. A. Jas and N. A. Touba, “Test vector decompression via cyclical scan chains and its application to testing core-based designs,” in Proceedings of the IEEE International Test Conference, pp. 458–464, Washington, DC, USA, October 1998. View at Scopus
  5. A. Chandra and K. Chakrabarty, “System-on-a-chip test-data compression and decompression architectures based on Golomb codes,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 20, no. 3, pp. 355–368, 2001. View at Publisher · View at Google Scholar · View at Scopus
  6. A. Chandra and K. Chakrabarty, “Frequency-directed run-length (FDR) codes with application to system-on-a-chip test data compression,” in Proceedings of the 19th IEEE VLSI Test Symposium, pp. 42–47, Marina Del Rey, Calif, USA, May 2001. View at Scopus
  7. A. H. El-Maleh, “Test data compression for system-on-a-chip using extended frequency-directed run-length code,” IET Computers and Digital Techniques, vol. 2, no. 3, pp. 155–163, 2008. View at Publisher · View at Google Scholar · View at Scopus
  8. H. G. Liang and C. Y. Jiang, “Efficient test data compression and decompression based on alternation and run length codes,” Chinese Journal of Computers, vol. 27, no. 4, pp. 548–554, 2004. View at Google Scholar · View at MathSciNet · View at Scopus
  9. W. Haifeng, Z. Wenfa, and C. Yifei, “Scheme of test data compression based on irrational number dictionary code,” Computer Engineering and Applications, vol. 50, no. 7, pp. 235–237, 2014. View at Google Scholar
  10. W. Zhan, H. Liang, C. Jiang, Z. Huang, and A. El-Maleh, “A scheme of test data compression based on coding of even bits marking and selective output inversion,” Computers & Electrical Engineering, vol. 36, no. 5, pp. 969–977, 2010. View at Publisher · View at Google Scholar · View at Scopus
  11. X.-J. Qian, 32-Bits Assembly Language Programming, China Machine Press, Beijing, China, 2011.
  12. W.-F. Zhan, H.-G. Liang, F. Shi, and Z.-F. Huang, “Test data compression scheme based on mixed fixed and variable length coding,” Chinese Journal of Computers, vol. 31, no. 10, pp. 1826–1834, 2008. View at Google Scholar · View at Scopus
  13. X.-Y. Peng and Y. Yu, “A test set compression algorithm based on Variable-Run-Length code,” Acta Electronica Sinica, vol. 35, no. 2, pp. 197–201, 2007. View at Google Scholar · View at Scopus
  14. A. Chandra and K. Chakrabarty, “Reduction of SOC test data volume, scan power and testing time using alternating run-length codes,” in Proceedings of the 39th Annual Design Automation Conference (DAC '02), pp. 673–678, June 2002. View at Publisher · View at Google Scholar · View at Scopus
  15. S. Hellebrand and A. Wurternberger, “Alternating run-length coding—a technique for improved test data compression,” in Proceedings of the 3rd IEEE International Workshop on Test Tesource Partitioning (TRP '02), IEEE Computer Society, Baltimore, Md, USA, October 2002.