Research Article
FPGA Implementation of Optimal 3D-Integer DCT Structure for Video Compression
Table 3
Device utilization summary.
| | Device utilization | Optimal integer set
10, 9, 6, 2, 3, 1, 1 | Sample integer set
13, 12, 5, 12, 0, 0, 12, 4, 3, 3, 4 |
| | Number of slice registers (out of 437200) | 975 | 1507 |
| | Number of slice LUT (out of 218600) | 5396 | 7054 |
| | Number of fully used LUT-FF pairs (out of 6014) | 357 | 146 |
| | Number of bonded IOBs (out of 250) | 213 | 269 |
| | Number of DSP slices (out of 900) | 22 | 120 |
| | Clock | 100 MHz | 104.46 MHz |
| Computational complexity
Multiplications/additions | 48/78 | 54/102 |
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