Low Power Systolic Array Based Digital Filter for DSP Applications

Table 1

Existing and proposed compressor architecture results.

Design	Compressor
	Existing [7]	Existing [6]	Existing (TSMC library compressor cell)	Proposed
Area	27.36	20.16	16.55	28.08
Delay	0.41	0.21	0.29	0.34
DP	6.12	5.125	4.37	4.977
LP	0.284	0.307	0.24	0.236
TP	6.404	5.432	4.61	5.213

Note: “area” in square microns; “delay” in nanoseconds; “DP” dynamic power in microwatt; “LP” leakage power in microwatt; “TP” total power in microwatt.