An Asynchronous Low Power and High Performance VLSI Architecture for Viterbi Decoder Implemented with Quasi Delay Insensitive Templates

Table 2

Comparison of parameters of asynchronous Viterbi decoder for various constraint lengths.

Parameters
Constraint length ()	Transistor count	Power consumption	Frequency	Delay
4	2116	50.47 mW	433 MHz	3 ms
5	3218	72.54 mW	452 MHz	2.21 ms
6	4320	83.80 mW	488 MHz	2.04 ms
7	5364	89.32 mW	530 MHz	1.88 ms