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The Scientific World Journal
Volume 2015, Article ID 749569, 10 pages
Research Article

NULL Convention Floating Point Multiplier

1Centre for Research, Anna University, Chennai, Tamilnadu 600025, India
2Faculty of Information and Communication Engineering, College of Engineering, Anna University, Chennai, Tamilnadu 600025, India

Received 2 October 2014; Revised 18 December 2014; Accepted 5 January 2015

Academic Editor: Shih-Hsu Huang

Copyright © 2015 Anitha Juliette Albert and Seshasayanan Ramachandran. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.


Floating point multiplication is a critical part in high dynamic range and computational intensive digital signal processing applications which require high precision and low power. This paper presents the design of an IEEE 754 single precision floating point multiplier using asynchronous NULL convention logic paradigm. Rounding has not been implemented to suit high precision applications. The novelty of the research is that it is the first ever NULL convention logic multiplier, designed to perform floating point multiplication. The proposed multiplier offers substantial decrease in power consumption when compared with its synchronous version. Performance attributes of the NULL convention logic floating point multiplier, obtained from Xilinx simulation and Cadence, are compared with its equivalent synchronous implementation.