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The Scientific World Journal
Volume 2015, Article ID 749569, 10 pages
Research Article

NULL Convention Floating Point Multiplier

1Centre for Research, Anna University, Chennai, Tamilnadu 600025, India
2Faculty of Information and Communication Engineering, College of Engineering, Anna University, Chennai, Tamilnadu 600025, India

Received 2 October 2014; Revised 18 December 2014; Accepted 5 January 2015

Academic Editor: Shih-Hsu Huang

Copyright © 2015 Anitha Juliette Albert and Seshasayanan Ramachandran. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Citations to this Article [1 citation]

The following is the list of published articles that have cited the current article.

  • T. Kalavathi Devi, and Sakthivel Palaniappan, “An Asynchronous Low Power and High Performance VLSI Architecture for Viterbi Decoder Implemented with Quasi Delay Insensitive Templates,” The Scientific World Journal, vol. 2015, pp. 1–13, 2015. View at Publisher · View at Google Scholar