Design Time Optimization for Hardware Watermarking Protection of HDL Designs

Table 4

Detailed synthesis results for Altera design tools and Apex20kc family.

IPP designs	DS	Spreading	HD	LEs	FSM LEs
1D-DWT FSM	DiTEC; MD5	RLA	91	6965	41
		SAMB	36	6947	37
		EPO	30	6963	36
	DiTEC; SHA1	RLA	102	6962	41
		SAMB	52	6945	33
		EPO	46	6940	31
	UGR; MD5	RLA	89	6969	41
		SAMB	37	6966	35
		EPO	33	6966	35
	UGR; SHA1	RLA	102	6960	43
		SAMB	49	6943	35
		EPO	49	6940	34
	FSU; MD5	RLA	93	6971	41
		SAMB	41	6949	37
		EPO	33	6964	37
	FSU; SHA1	RLA	106	6963	40
		SAMB	41	6935	34
		EPO	37	6935	32
1D-DWT LFSR	DiTEC; MD5	RLA	91	6995	19
		SAMB	36	6981	15
		EPO	30	6974	14
	DiTEC; SHA1	RLA	102	7050	29
		SAMB	52	7018	20
		EPO	46	7007	21
	UGR; MD5	RLA	89	7026	18
		SAMB	37	6985	15
		EPO	33	6981	14
	UGR; SHA1	RLA	102	7042	31
		SAMB	49	7013	23
		EPO	49	7003	19
	FSU; MD5	RLA	93	7009	18
		SAMB	41	6985	15
		EPO	33	6980	15
	FSU; SHA1	RLA	106	7041	29
		SAMB	41	6999	21
		EPO	37	6996	19