Table of Contents
VLSI Design
Volume 1, Issue 1, Pages 9-22

Theory, Analysis and Implementation of an On-Line BIST Technique

1Cadence Design Systems Inc., Lowell, Massachusetts, USA
2Department of Electrical and Computer Engineering, University of Wisconsin, Madison, Wisconsin, USA

Copyright © 1993 Hindawi Publishing Corporation. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.


A Built-ln Concurrent Self-Test (BICST) technique for testing combinational logic circuits concurrently with their normal operation is proposed. Concept of sharing the test hardware between identical circuits to reduce the overall area overhead is introduced. The method was implemented in the design of an ALU with on-line test capability in CMOS technology. The additional hardware used for a 12-bit ALU was 19% of the total chip area and it did not impose any timing overhead on the operation of the ALU. The overhead decreases with an increase in the size of the ALU.

Following the description of the BICST technique, measures for evaluating the performance of the BICST technique are defined. Methods for the computation of the performance measures using analytical and simulation techniques are discussed and results of these methods are reported. Methods for detecting intermittent faults and for computing the transient fault coverage using BICST are also described. The impact of BICST on the system diagnostics and system maintenance is discussed.