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VLSI Design
Volume 1 (1993), Issue 1, Pages 71-85

Coverage of Node Shorts Using Internal Access and Equivalence Classes

Rome Laboratory (RL/ERDA), Griffiss AFB, New York, USA

Copyright © 1993 Hindawi Publishing Corporation. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.


A method is presented that determines the coverage of shorts (bridging failures) in digital logic circuits by internal access test techniques. These are test techniques that provide observability of circuit nodes, such as CMOS power supply current monitoring (including IDDQ), CrossCheck, and voltage contrast. Only fault-free circuit simulation is used to obtain node states. Two versions of the algorithm are presented: a simple algorithm that is suitable for use with two-state logic (0 and 1), and a more general algorithm for four-state logic (0, 1, X, and Z). The result is a set of sets of nodes, where a list of all potential shorts that could exist in the circuit yet be undetected after testing is obtained easily from the power sets of these sets; unlike other approaches the full universe of potential shorts is not generated. Experiments show that short, randomly generated sequences of test vectors detect essentially all detectable shorts of multiplicity 2 for both combinational and sequential circuits.