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VLSI Design
Volume 1, Issue 1, Pages 1-7
http://dx.doi.org/10.1155/1993/76586

Overlapped Subarray Segmentation: An Efficient Test Method for Cellular Arrays

Department of Electrical and Computer Engineering, University of Texas, Austin, Texas, USA

Copyright © 1993 Hindawi Publishing Corporation. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Abstract

This paper presents a new test approach that is suitable for repetitive structures such as cellular arrays. As such, it is directly applicable to most arithmetic circuits which are generally quite regular. It is based on exhaustive testing of overlapping segments of the array. This approach detects bridging faults in addition to stuck-at faults. Such bridging faults are a significant problem in arithmetic circuits. The ability to detect arbitrary faults involving any cells within a designer selected distance (i.e., the diameter of the subset that is exhaustively tested) is unique to this testing approach. The high coverage of the proposed technique makes it attractive for testing current VLSI and future WSI arrays.