VLSI Design

VLSI Design / 1994 / Article
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Digital Hardware Testing

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Volume 1 |Article ID 027973 | https://doi.org/10.1155/1994/27973

Yashwant K. Malaiya, Anura P. Jayasumana, Carol Q. Tong, Sankaran M. Menon, "Resolution Enhancement in IDDQ Testing for Large ICs", VLSI Design, vol. 1, Article ID 027973, 8 pages, 1994. https://doi.org/10.1155/1994/27973

Resolution Enhancement in IDDQ Testing for Large ICs


Current drawn by a static CMOS VLSI integrated circuit during quiescent periods is extremely small and is normally of the order of nanoamperes. However, it is remarkably susceptible to a number of failure modes. Many faults present in such ICs cause the quiescent power-supply current (IDDQ) to increase by several orders of magnitude. Some of these faults may not manifest themselves as logical faults, and would not be detected by traditional IC test techniques.In large ICs, it may be hard to distinguish between larger IDDQ due to defects and elevated IDDQ due to normal parameter variations. A statistical characterization of the problem is presented. This can be used to determine the optimal size of partitions. A new information compression scheme is presented which can significantly enhance resolution.

Copyright © 1994 Hindawi Publishing Corporation. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

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