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VLSI Design
Volume 2, Issue 3, Pages 233-239
http://dx.doi.org/10.1155/1994/32902

TOPS: A Target-Oriented Partial Scan Design Package Based on Simulated Annealing

Department of Electrical Engineering, Indian Institute of Technology, New Delhi 110016, India

Received 3 December 1992; Revised 22 March 1993

Copyright © 1994 Hindawi Publishing Corporation. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

How to Cite this Article

C. P. Ravikumar and H. Rasheed, “TOPS: A Target-Oriented Partial Scan Design Package Based on Simulated Annealing,” VLSI Design, vol. 2, no. 3, pp. 233-239, 1994. https://doi.org/10.1155/1994/32902.