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VLSI Design
Volume 1 (1994), Issue 2, Pages 155-167

Geometric Design Rule Check of VLSI Layouts in Distributed Computing Environment

Laboratory for Computer Aided Design, Super Computer Education and Research Center, Indian Institute of Science, Bangalore, India

Received 11 May 1989; Revised 18 September 1990

Copyright © 1994 Hindawi Publishing Corporation. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.


In this paper we provide a distributed solution to perform Design Rule Checking (DRC) of a layout by exploiting either spatial independence or layer independence in layout data. We show that the former approach to DRC can result in reasonable speedup only for large layouts, whereas, the latter approach shows a better performance for smaller layouts. We also provide an algorithm to optimally partition a layout and a scheme to allocate DRC tasks to idle processors in a Distributed Computing Environment (DCE) to attain load balancing.