Table of Contents
VLSI Design
Volume 2, Issue 2, Pages 89-103

Technology Mapping for FPGA Using Generalized Functional Decomposition

1Department of Computer Science and Information Engineering, National Chiao Tung University, HsinChu 30050, Taiwan
2Department of Computer Science, National Tsing Hua University, HsinChu 30043, Taiwan

Copyright © 1994 Hindawi Publishing Corporation. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.


In this paper, we address the technology mapping for RAM-based FPGA. Functional decomposition is applied to decompose a large function into a set of smaller subfunctions such that each subfunction can be implemented using a single logic cell. Our system is mainly divided into two parts. The first part is designed specifically for totally symmetric functions. A Fast-Decompose algorithm based on weight dependency is proposed. The second part deals with general functions. We consider some techniques such as output partition, variable partition, don't care assignment and encoding to minimize the number of subfunctions derived. Using these techniques together, our tool, Fun-Map, improves the mapping results compared with other tools in terms of area and delay.