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VLSI Design
Volume 1, Issue 3, Pages 243-259
http://dx.doi.org/10.1155/1994/67035

Block-Level Logic Extraction from CMOS VLSI Layouts

Department of Electrical Engineering, Virginia Polytechnic Institute and State University, Blacksburg, VA, USA

Received 30 August 1990; Revised 21 February 1991

Copyright © 1994 Hindawi Publishing Corporation. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

How to Cite this Article

Inderpreet Bhasin and Joseph G. Tront, “Block-Level Logic Extraction from CMOS VLSI Layouts,” VLSI Design, vol. 1, no. 3, pp. 243-259, 1994. https://doi.org/10.1155/1994/67035.