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VLSI Design
Volume 2, Issue 3, Pages 199-207
http://dx.doi.org/10.1155/1994/71941

An Efficient Automatic Test Pattern Generator for Stuck-Open Faults in CMOS Combinational Circuits

The Bradley Department of Electrical Engineering, Virginia Polytechnic Institute, State University, Blacksburg 24061, Virginia, USA

Received 15 November 1990; Revised 8 March 1991

Copyright © 1994 Hindawi Publishing Corporation. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Abstract

In this paper, we describe a highly efficient automatic test pattern generator for stuck-open (SOP) faults, called SOPRANO, in CMOS combinational circuits. The key idea of SOPRANO is to convert a CMOS circuit into an equivalent gate level circuit and SOP faults into the equivalent stuck-at faults. Then SOPRANO derives test patterns for SOP faults using a gate level test pattern generator. Several techniques to reduce the test set size are introduced in SOPRANO. Experimental results performed on eight benchmark circuits show that SOPRANO achieves high SOP fault coverage and short processing time.