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VLSI Design
Volume 3 (1995), Issue 3-4, Pages 301-313
http://dx.doi.org/10.1155/1995/24594

Multi-Level Logic Synthesis Based on Kronecker Decision Diagrams and Boolean Ternary Decision Diagrams for Incompletely Specified Functions

1Department of Electrical Engineering, Portland State University, Portland 97207, OR, USA
2Arkos Design Inc., 5619 Scotts Valley Drive, Scotts Valley 95066, CA , USA

Copyright © 1995 Hindawi Publishing Corporation. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

How to Cite this Article

Marek A. Perkowski, Malgorzata Chrzanowska-Jeske, Andisheh Sarabi, and Ingo Schäfer, “Multi-Level Logic Synthesis Based on Kronecker Decision Diagrams and Boolean Ternary Decision Diagrams for Incompletely Specified Functions,” VLSI Design, vol. 3, no. 3-4, pp. 301-313, 1995. doi:10.1155/1995/24594