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VLSI Design
Volume 3, Issue 1, Pages 43-51
http://dx.doi.org/10.1155/1995/26912

Performance and Area Optimization of VLSI Systems Using Genetic Algorithms

Department of Electrical Engineering, Colorado State University, Ft. Collins 80523, CO, USA

Received 26 July 1993; Accepted 21 March 1994

Copyright © 1995 Hindawi Publishing Corporation. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Abstract

A new performance and area optimization algorithm for complex VLSI systems is presented. It is widely believed within the VLSI CAD community that the relationship between delay and silicon area of a VLSI chip is convex. This conclusion is based on a simplified linear RC model to predict gate delays. In the proposed optimization algorithm, a nonlinear, non-RC based transistor delay model was used which resulted in a non-convex relationship between the delay and the silicon area of a VLSI chip. Genetic algorithms are better suited for discrete, non-convex, non-linear optimization problems than traditional calculus-based algorithms. By using the genetic algorithms in the performance and area optimization, we are able to find the optimal values for both delay and silicon area for the ISCAS benchmark circuits.