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VLSI Design
Volume 2, Issue 4, Pages 287-303
http://dx.doi.org/10.1155/1995/45809

Design of Components for a Low Cost Combining Switch

Courant Institute of Mathematical Sciences, New York University, USA

Copyright © 1995 Hindawi Publishing Corporation. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Abstract

We present the design for the two VLSI components used in a processor-to-memory interconnection network for a shared memory system. These components allow the combining of requests that are destined to the same memory location. The design contains both semi-systolic queues and an associative “wait buffer.” Transition equations and schematics of the critical pieces of the design are included.