Table of Contents
VLSI Design
Volume 2, Issue 4, Pages 375-388

Designing Interconnection Networks for Multi-level Packaging

Computer Science Division, University of California at Berkeley, Berkeley 94720, CA, USA

Copyright © 1995 Hindawi Publishing Corporation. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Citations to this Article [1 citation]

The following is the list of published articles that have cited the current article.

  • A Jayadevan, and Lm Patnaik, “Fault-tolerant characteristics and topological properties of a hierarchical network of hypercubes,” International Journal Of High Speed Computing, vol. 10, no. 1, pp. 1–17, 1999. View at Publisher · View at Google Scholar