Table of Contents Author Guidelines Submit a Manuscript
VLSI Design
Volume 3 (1995), Issue 3-4, Pages 289-300
http://dx.doi.org/10.1155/1995/67208

A General Approach to Boolean Function Decomposition and its Application in FPGABased Synthesis

Warsaw University of Technology, Institute of Telecommunications, Nowowiejska 15/19, Warsaw 00-665, Poland

Copyright © 1995 Hindawi Publishing Corporation. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Citations to this Article [17 citations]

The following is the list of published articles that have cited the current article.

  • Blaž Zupana, Marko Bohanec, Janez Demšar, and Ivan Bratko, “Learning by discovering concept hierarchies,” Artificial Intelligence, vol. 109, no. 1, pp. 211–242, 1999. View at Publisher · View at Google Scholar
  • Mariusz Rawski, Lech Jóźwiak, and Tadeusz Luba, “Functional decomposition with an efficient input support selection for sub-functions based on information relationship measures,” Journal of Systems Architecture, vol. 47, no. 2, pp. 137–155, 2001. View at Publisher · View at Google Scholar
  • L. Józwiak, and A. Slusarczyk, “General decomposition of incompletely specified sequential machines with multi-state behavior realization,” Journal of Systems Architecture, vol. 50, no. 8, pp. 445–492, 2004. View at Publisher · View at Google Scholar
  • Paweł Tomaszewicz, Mariusz Rawski, and Piotr Zbysiński, “B06: Advanced synthesis of digital filters based on distributed arithmetic concept for FPGAs,” IFAC Proceedings Volumes, vol. 37, no. 20, pp. 198–202, 2004. View at Publisher · View at Google Scholar
  • Mariusz Rawski, Henry Selvaraj, and Tadeusz Luba, “An application of functional decomposition in ROM-based FSM implementation in FPGA devices,” Journal of Systems Architecture, vol. 51, no. 6-7, pp. 424–434, 2005. View at Publisher · View at Google Scholar
  • Mariusz Rawski, Paweł Tomaszewicz, Henry Selvaraj, and Tadeusz Łuba, “Efficient implementation of digital filters with use of advanced synthesis methods targeted FPGA architectures,” Proceedings - DSD'2005: 8th Euromicro Conference on Digital System Design - Architectures, Methods and Tools, vol. 2005, pp. 460–466, 2005. View at Publisher · View at Google Scholar
  • Shruti Patil, and V. Muthukumar, “Simultaneous column minimization-encoding approach for serial decomposition,” Proceedings - Sixth International Conference on Computational Intelligence and Multimedia Applications, ICCIMA 2005, pp. 159–165, 2005. View at Publisher · View at Google Scholar
  • Venkatesan Muthukumar, Robert J. Bignall, and Henry Selvaraj, “An efficient variable partitioning approach for functional decomposition of circuits,” Journal of Systems Architecture, vol. 53, no. 1, pp. 53–67, 2007. View at Publisher · View at Google Scholar
  • P. Tomaszewicz, M. Nowicka, B. Falkowski, and T. Łuba, “Logic synthesis importance in FPGA-based designing of image and signal processing systems,” Proceedings of the 14th International Conference "Mixed Design of Integrated Circuits and Systems", MIXDES 2007, pp. 141–146, 2007. View at Publisher · View at Google Scholar
  • Pawel Morawiecki, Mariusz Rawski, and Henry Selvaraj, “Application of functional decomposition in synthesis of boolean function sets,” Proceedings of 19th International Conference on Systems Engineering, ICSEng 2008, pp. 350–355, 2008. View at Publisher · View at Google Scholar
  • Stefan Kolłodziński, and Edward Hrynkiewicz, “An utilisation of boolean differential calculus in variables partition calculation for decomposition of logic functions,” Proceedings of the 2009 IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2009, pp. 34–37, 2009. View at Publisher · View at Google Scholar
  • Edward Hrynkiewicz, and Stefan Kołodziński, “Non-disjoint decomposition of logic functions in Reed-Muller spectral domain,” Proceedings of the 13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2010, pp. 293–296, 2010. View at Publisher · View at Google Scholar
  • Mariusz Rawski, “Application of Indexed Partition Calculus in Logic Synthesis of Boolean Functions for FPGAs,” International Journal of Electronics and Telecommunications, vol. 57, no. 2, 2011. View at Publisher · View at Google Scholar
  • Huan Chen, and Joao Marques-Silva, “Improvements to satisfiability-based boolean function bi-decomposition,” 2011 IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, VLSI-SoC 2011, pp. 142–147, 2011. View at Publisher · View at Google Scholar
  • Stefan Kołodziński, and Edward Hrynkiewicz, “Decomposition of multi-output logic function in Reed-Muller spectral domain,” Proceedings of the 2011 IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2011, pp. 179–182, 2011. View at Publisher · View at Google Scholar
  • Dariusz Polok, and Edward Hrynkiewicz, “Some Observations Related to Searching for Logic Functions Decomposition in Reed-Muller Spectral Domain,” IFAC-PapersOnLine, vol. 49, no. 25, pp. 104–108, 2016. View at Publisher · View at Google Scholar
  • Kubica, and Kania, “Decomposition of multi-output functions oriented to configurability of logic blocks,” Bulletin of the Polish Academy of Sciences: Technical Sciences, vol. 65, no. 3, pp. 317–331, 2017. View at Publisher · View at Google Scholar