In this work, the design and implementation of a low power ternary full adder are presented in CMOS technology. In a ternary full adder design, the basic building blocks, the positive ternary inverter (PTI) and negative ternary inverter (NTI) are developed using a CMOS inverter and pass transistors. In designs of PTI and NTI, W/L ratios of transistors have been varied for their optimum performance. The ternary full adder and its building blocks have been simulated with SPICE 2G.6 using the MOSIS model parameters. The rise and fall times of PTI show an improvement by a factor of 14 and 4, respectively, and that of the NTI by a factor of nearly 4 and 17, respectively over that of earlier designs implemented in depletion-enhancement CMOS (DECMOS) technology. The noise margins improve by a factor of nearly 2 in PTI and NTI, respectively.The ternary full adder has been fabricated in MOSIS two micron n-well CMOS technology. The full adder and its building blocks, NTI and PTI have been tested experimentally for static and dynamic performance, compared with the SPICE simulated behavior, and close agreement is observed.The ternary-valued logic circuits designed in the present work which do not use depletion mode MOSFETS perform better than that implemented earlier in DECMOS technology. The present design is fully compatible with the current CMOS technology, uses fewer components and dissipates power in the microwatt range.

A.  Srivastava

K.  Venkatapathy

Design and Implementation of a Low Power Ternary Full Adder

We base our approach to the design of complex logic ICs on four premises:Design of a chip&#39;s abstract architecture&#8212;its major components, their tasks, and theirintercommunication&#8212;should precede definition of its functionality.Graphics is ideal for representing abstract architectures; text is better for functionality.The designer should not have to translate graphical information into text.Graphical and textual design capture can be integrated with synthesis.

Murray W. Pearson

Paul J. Lyons

Mark D. Apperley

High-Level Graphical Abstraction in Digital Design

This paper presents an overview of Zener zap anti-fuse trim as used to achieve improvedaccuracy in precision integrated circuits. Because this technology spans design and manufacturing,elements of design, layout, processing, and testing are included. The mechanism isdefined and typical applications are discussed. Layout considerations of anti-fuse devices aresummarized and complex trim networks and multiplexed control methods are presented.Both bipolar and CMOS process implementations are considered. The paper also contains abibliography which includes U.S. patents, which make up a large part of the technicaldocumentation of this technology.

Donald T. Comer

Zener Zap Anti-Fuse Trim in VLSI Circuits

The present work involves integration of the simulation stage of design of a VLSI circuit and its testing stage. The SPICE simulator, TEK LV500 ASIC Design Verification System, and TekWaves, a test program generator for LV500, were integrated. A software interface in &#8216;C&#8217; language in UNIX &#8216;solaris 1.x&#8217; environment has been developed between SPICE and the testing tools (TekWAVES and LV500). The function of the software interface developed is multifold. It takes input from either SPICE2G.6 or SPICE 3e.1. The output generated by the interface software can be given as an input to either TekWAVES or LV500. A graphical user interface has also been developed with OPENWlNDOWS using Xview tool kit on SUN workstation. As an example, a two phase clock generator circuit has been considered and usefulness of the software demonstrated. The interface software could be easily linked with VLSI design such as MAGIC layout editor.

S. R. Palavali

Integration of SPICE with TEK LV500 ASIC Design Verification System

In this paper, we describe TOGAPS, a Testability-Oriented Genetic Algorithm for Pipeline
Synthesis. The input to TOGAPS is an unscheduled data flow graph along with a specification
of the desired pipeline latency. TOGAPS generates a register-level description of a
datapath which is near-optimal in terms of area, meets the latency requirement, and is highly
testable. Genetic search is employed to explore a 3-D search space, the three dimensions
being the chip area, average latency, and the testability of the datapath. Testability of a
design is evaluated by counting the number of self-loops in the structure graph of the data
path. Each design is characterized by a four-tuple consisting of (i) the latency and schedule
information, (ii) the module allocation, (iii) operation-to-module binding, and (iv) value-to-register
binding. Accordingly, we maintain the population of designs in a hierarchical manner.
The topmost level of this hierarchy consists of the latency and schedule information,
which together characterize the timing performance of the design. The middle level of the
hierarchy consists of a number of allocations for a given latency/schedule duplet. The lowest
level of the hierarchy consists of a number of bindings for a specific latency/schedule/
allocation. An initial population of designs is constructed from the given data flow graph
using different latency cycles whose average latency is in the specified range. Multiple
scheduling heuristics are used to generate schedules for the DFG. For each of the resulting
scheduled data flow graphs, we decide on an allocation of modules and registers based on a
lower bound estimated using the schedule and latency information. The operation-to-module
binding and the value-to-register binding are then carried out. A fitness measure is evaluated
for each of the resulting data paths; this fitness measure includes one component for each of
the three search dimensions. Crossover and mutation operators are used to generate new
designs from the current set of parent designs. The crossover operator attempts to combine
the properties of two designs. The mutation operators include addition and deletion of pure
delays before scheduling, as well as changes in the register and module allocation prior to
binding. The genetic algorithm applies the rule of the survival of the fittest to obtain nearoptimal
solution to the otherwise intractable problem of data path synthesis. We have implemented
TOGAPS on a Sun/SPARC 10 and studied its performance on a number of
benchmark examples. Results indicate that TOGAPS finds area-optimal datapaths for the
specified latency cycle, while reducing the number of self-loops in the data path.

C. P. Ravikumar

V. Saxena

TOGAPS: A Testability Oriented Genetic Algorithm For Pipeline Synthesis

The development of multi-processor architectures requires extensive behavioral simulations to verify the correctness of design and to evaluate its performance. A high level language can provide maximum flexibility in this respect if the constructs for handling concurrent processes and a time mapping mechanism are added. This paper describes a novel technique for emulating hardware processes involved in a parallel architecture such that an object-oriented description of the design is maintained. The communication and synchronization between hardware processes is handled by splitting the processes into their equivalent subprograms at the entry points. The proper scheduling of these subprograms is coordinated by a timing wheel which provides a time mapping mechanism. Finally, a high level language pre-processor is proposed so that the timing wheel and the process emulation details can be made transparent to the user.

Ausif Mahmood

Behavioral Simulation and Performance Evaluation of Multi-Processor Architectures

Testability should be considered as early as possible in VLSI synthesis and optimization. Inmost CAD tools, testability preservation is achieved as a by-product of finding a less redundantimplementation. Unfortunately, this approach is not supported by theory. It is essentialto have an optimization scheme that systematically preserves testability. A complete theorycovering testability-preserving optimization of combinational circuits is yet to be developed.In this paper, a new testability-preserving theory is established. This theory covers mostoptimization cases in the synthesis of irredundant circuits. Optimization of redundant circuitsis also considered. Algorithms based on this theory are proposed. Experiments to verify thetheory and algorithms are reported. The developed theory and algorithms are more generalthan previous results.

Jiabi  Zhu

Mostafa  Abd-El-Barr

Carl  McCrosky

A New Theory for Testability-Preserving Optimization ofCombinational Circuits

The routing problem in VLSI-layout can be modeled as a problem of packing node-disjoint Steiner trees in a graph. The problem is as follows: Given an undirected network G &#61; (V, E) and a net list &#936; <mml:math xmlns:mml="http://www.w3.org/1998/Math/MathML"><mml:mrow><mml:mo>&#x007B;</mml:mo><mml:msub><mml:mi>N</mml:mi><mml:mi>i</mml:mi></mml:msub><mml:mo>,</mml:mo><mml:mtext>&#x2009;</mml:mtext><mml:mi>i</mml:mi><mml:mtext>&#x2009;</mml:mtext><mml:mo>=</mml:mo><mml:mtext>&#x2009;</mml:mtext><mml:mn>1</mml:mn><mml:mo>,</mml:mo><mml:mn>...</mml:mn><mml:mo>,</mml:mo><mml:mtext>&#x2009;</mml:mtext><mml:mi>r</mml:mi><mml:mo>&#x007D;</mml:mo></mml:mrow></mml:math>, a family <mml:math xmlns:mml="http://www.w3.org/1998/Math/MathML"><mml:mrow><mml:msub><mml:mi>&#x0393;</mml:mi><mml:mi>G</mml:mi></mml:msub><mml:mo>=</mml:mo><mml:mo>&#x007B;</mml:mo><mml:msub><mml:mi>T</mml:mi><mml:mrow><mml:msub><mml:mi>N</mml:mi><mml:mi>i</mml:mi></mml:msub></mml:mrow></mml:msub><mml:mtext>&#x2009;</mml:mtext><mml:mo>=</mml:mo><mml:mtext>&#x2009;</mml:mtext><mml:mo stretchy="false">(</mml:mo><mml:msub><mml:mi>V</mml:mi><mml:mrow><mml:msub><mml:mi>N</mml:mi><mml:mi>i</mml:mi></mml:msub><mml:mtext>&#x2009;</mml:mtext></mml:mrow></mml:msub><mml:mo>,</mml:mo><mml:mtext>&#x2009;</mml:mtext><mml:msub><mml:mi>E</mml:mi><mml:mrow><mml:msub><mml:mi>N</mml:mi><mml:mi>i</mml:mi></mml:msub></mml:mrow></mml:msub><mml:mo stretchy="false">)</mml:mo><mml:mo>,</mml:mo><mml:mtext>&#x2009;</mml:mtext><mml:mi>i</mml:mi><mml:mtext>&#x2009;</mml:mtext><mml:mo>=</mml:mo><mml:mtext>&#x2009;</mml:mtext><mml:mn>1</mml:mn><mml:mo>,</mml:mo><mml:mn>...</mml:mn><mml:mo>,</mml:mo><mml:mtext>&#x2009;</mml:mtext><mml:mi>r</mml:mi><mml:mo>&#x007D;</mml:mo></mml:mrow></mml:math> is a node-disjoint family of Steiner trees spanning &#936; if <mml:math xmlns:mml="http://www.w3.org/1998/Math/MathML"><mml:mrow><mml:msub><mml:mi>T</mml:mi><mml:mrow><mml:msub><mml:mi>N</mml:mi><mml:mi>i</mml:mi></mml:msub></mml:mrow></mml:msub></mml:mrow></mml:math>, is a Steiner tree spanning <mml:math xmlns:mml="http://www.w3.org/1998/Math/MathML"><mml:mrow><mml:msub><mml:mi>N</mml:mi><mml:mi>i</mml:mi></mml:msub></mml:mrow></mml:math> for i &#61; 1, ..., r and <mml:math xmlns:mml="http://www.w3.org/1998/Math/MathML"><mml:mrow><mml:msub><mml:mi>V</mml:mi><mml:mrow><mml:msub><mml:mi>N</mml:mi><mml:mi>i</mml:mi></mml:msub></mml:mrow></mml:msub><mml:mtext>&#x2009;</mml:mtext><mml:mo>&#x2229;</mml:mo><mml:mtext>&#x2009;</mml:mtext><mml:msub><mml:mi>V</mml:mi><mml:mrow><mml:msub><mml:mi>N</mml:mi><mml:mi>j</mml:mi></mml:msub></mml:mrow></mml:msub></mml:mrow></mml:math> &#61; for i &#8800; j. The edge-disjoint version of this problem is known to be NP-hard for t. series-parallel graphs (see Rlchey and Parker [5]). In this paper we give a <mml:math xmlns:mml="http://www.w3.org/1998/Math/MathML"><mml:mrow><mml:mi>O</mml:mi><mml:mo stretchy="false">(</mml:mo><mml:msup><mml:mi>n</mml:mi><mml:mn>5</mml:mn></mml:msup><mml:mo stretchy="false">)</mml:mo></mml:mrow></mml:math> algorithm for finding a minimum-cost node-disjoint family of Steiner trees in series-parallel networks. Our algorithm can be extended to k-trees and is polynomial for fixed k.

Sunil  Chopra

Kalyan T. Talluri

Minimum-Cost Node-Disjoint Steiner Trees in Series-Parallel Networks

The split k-layer (k &#8805; 2) circular topological via minimization (k-CTVM) problem is reconsidered here. The problem is finding a topological routing of the n nets, using k available layers, such that the total number of vias is minimized. The optimal solution of this problem is solved in <mml:math xmlns:mml="http://www.w3.org/1998/Math/MathML"><mml:mrow><mml:mi>O</mml:mi><mml:mo stretchy="false">(</mml:mo><mml:msup><mml:mi>n</mml:mi><mml:mrow><mml:mn>2</mml:mn><mml:mi>k</mml:mi><mml:mo>+</mml:mo><mml:mn>1</mml:mn></mml:mrow></mml:msup><mml:mo stretchy="false">)</mml:mo></mml:mrow></mml:math> time. However, such an algorithm is inefficient even for n &#8805; 8 and k &#8805; 2. A heuristic algorithm with complexity of <mml:math xmlns:mml="http://www.w3.org/1998/Math/MathML"><mml:mrow><mml:mi>O</mml:mi><mml:mo stretchy="false">(</mml:mo><mml:mi>k</mml:mi><mml:mtext>&#x2009;</mml:mtext><mml:msup><mml:mi>n</mml:mi><mml:mn>4</mml:mn></mml:msup><mml:mo stretchy="false">)</mml:mo></mml:mrow></mml:math> is presented. When the experimental results of this algorithm and that of an exhaustive algorithm are compared, the same number of optimal solutions is obtained from this heuristic algorithm for all permutations of 1) n &#61; 8 with k &#61; 2 or 3, and 2) n &#61; 10 with k &#61; 3. For other cases, the number of optimal solutions from this algorithm depends on the permutations been selected; and this number, in general, will increase as k increases.

J. S. Huang

Y. H. Chin

An Efficient Algorithm for the Split K-Layer Circular Topological Via Minimization Problem

The problem of modifying a synthesized circuit to improve its path sensitizability has beeninvestigated. It is shown that a large number of paths, that cannot be sensitized using single-transitiontests, are redundant paths and they can be removed by appropriate modification ofthe circuit. The effect of these modifications on area and performance of the circuit has beenanalyzed. For the paths which are neither redundant nor sensitizable using single-transitiontests, it is shown that they can be sensitized using multiple-transition tests. Results obtainedon some common benchmark examples suggest the validity and viability of this approach.

Bhanu  Kapoor

V. S. S. Nair

Improving Path Sensitizability ofCombinational Circuits

Placement is an important constrained optimization problem in the design of very large scale
(VLSI) integrated circuits [1–4]. Simulated annealing [5] and min-cut placement [6] are two
of the most successful approaches to the placement problem. Min-cut methods yield less
congested and more routable placements at the expense of more wire-length, while simulated
annealing methods tend to optimize more the total wire-length with little emphasis on the
minimization of congestion. It is also well known that min-cut algorithms are substantially
faster than simulated-annealing-based methods. In this paper, a fast min-cut algorithm
(ROW-PLACE) for row-based placement is presented and is empirically shown to achieve
simulated-annealing-quality wire-length on a number of benchmark circuits. In comparison
with Timberwolf 6 [7], ROW-PLACE is at least 12 times faster in its normal mode and is at
least 25 times faster in its faster mode. The good results of ROW-PLACE are achieved using
a very effective clustering-based partitioning algorithm in combination with constructive
methods that reduce the wire-length of nets involved in terminal propagation.

Youssef Saab

A Fast Clustering-Based Min-Cut Placement Algorithm
With Simulated-Annealing Performance

The compaction step of integrated circuit design motivates associating several kinds of graphs with a collection of non-overlapping rectangles in the plane. These graphs are intended to capture various visibility relations amongst the rectangles in the collection. The contribution of this paper is to propose time- and cost-optimal algorithms to construct two such graphs, namely, the dominance graph (DG, for short) and the visibility graph (VG, for short). Specifically, we show that with a collection of n non-overlapping rectangles as input, both these structures can be constructed in &#952;(log n) time using n processors in the CREW model.

D.  Bhagavathi

H.  Gurla

S.  Olariu

J. L. Schwing

J.  Zhang

Time- and Cost-Optimal Parallel Algorithms for the Dominance and Visibility Graphs

In this paper we present a simple but efficient timing-driven placement algorithm for FPGAs. The algorithm computes forces acting on a logic block in the FPGA to determine its relative location with respect to other blocks. The forces depend on the criticality of nets shared between the two blocks. Unlike other net-based approaches, timing constraints are incorporated directly into the force equations to guide the placement. Slot assignment is then used to move the blocks into valid slot locations on the FPGA chip. The assignment algorithm also makes use of the delay information of nets so that the final placement is able to meet the timing criteria specified for the circuit. The novelty of the approach lies in the formulation of the force equations and the manner in which weights of the nets are dynamically altered to influence the placement. Experiments conducted on industrial test circuits and MCNC circuits give very promising results and indicate that the algorithm succeeds in significantly reducing the maximum delay in the circuit. In addition, routability is not adversely affected and running time is low.

Srilata Raman

C. L. Liu

Larry G. Jones

Timing-Constrained FPGA Placement: A Force-Directed Formulation and Its Performance Evaluation

This paper presents a new Field-Programmable Gate Array (FPGA) architecture which reduces the density gap between FPGAs and Mask-Programmed Gate Arrays (MPGAs) for datapath oriented circuits. This is primarily achieved by operating on data as a number of identically programmed four-bit slices. The interconnection network incorporates distinct sets of resources for routing control and data signals. These features reduce circuit area by sharing programming bits among four-bit slices, reducing the total number of storage cells required.This paper discusses the requirements of logic blocks and routing structures that can be used to implement typical circuits containing a number of regularly structured datapaths of various sizes, as well as a small number of irregularities. It proposes a specific set of logic block architectures and analyzes it empirically. Experimental results show that the block with the smallest estimated area contains the following features: a lookup table with four read ports, a dedicated carry chain using a bidirectional four-bit carry skip circuit, a four-bitregister with enable and direct input capabilities, and four three-state buffers. Further estimates of implementation area predict that the area of a design&#39;s datapath can be reduced by a factor of approximately two compared to a conventional FPGA through the use of programming bit sharing.

Don  Cherepacha

David  Lewis

DP-FPGA: An FPGA Architecture Optimized for Datapaths

Field-programmable systems with multiple FPGAs on a PCB or an MCM are being used by system designers when a single FPGA is not sufficient. We address the problem of partitioning a large technology mapped FPGA circuit onto multiple FPGA devices of a specific target technology. The physical characteristics of the multiple FPGA system (MFS) pose additional constraints to the circuit partitioning algorithms: the capacity of each FPGA, the timing constraints, the number of I/Os per FPGA, and the pre-designed interconnection patterns of each FPGA and the package. Existing partitioning techniques which minimize just the cut sizes of partitions fail to satisfy the above challenges. We therefore present a timing driven N-way partitioning algorithm based on simulated annealing for technology-mapped FPGA circuits. The signal path delays are estimated during partitioning using a timing model specific to a multiple FPGA architecture. The model combines all possible delay factors in a system with multiple FPGA chips of a target technology. Furthermore, we have incorporated a new dynamic net-weighting scheme to minimize the number of pin-outs for each chip. Finally, we have developed a graph-based global router for pin assignment which can handle the pre-routed connections of our MFS structure. In order to reduce the time spent in the simulated annealing phase of the partitioner, clusters of circuit components are identified by a new linear-time bottom-up clustering algorithm. The annealing-based N-way partitioner executes four times faster using the clusters as opposed to a flat netlist with improved partitioning results. For several industrial circuits, our approach outperforms the recursive min-cut bi-partitioning algorithm by 35&#37; in terms of nets cut. Our approach also outperforms an industrial FPGA partitioner by 73&#37; on average in terms of unroutable nets. Using the performance optimization capabilities in our approach we have successfully partitioned the MCNC benchmarks satisfying the critical path constraints and achieving a significant reduction in the longest path delay. An average reduction of 17&#37; in the longest path delay was achieved at the cost of 5&#37; in total wire length.

Kalapi  Roy

Carl  Sechen

A Timing-Driven Partitioning System for Multiple FPGAs

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