Table of Contents
VLSI Design
Volume 4, Issue 2, Pages 135-139

The Use of Field-Programmable Gate Arrays for the Hardware Acceleration of Design Automation Tasks

1Department of Electronics, University of York, York YO1 5DD, UK
2Department of Electrical Engineering and Electronics, UMIST, Manchester M60 1QD, UK

Copyright © 1996 Hindawi Publishing Corporation. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.


This paper investigates the possibility of using Field-Programmable Gate Arrays (Fpgas) as reconfigurable co-processors for workstations to produce moderate speedups for most tasks in the design process, resulting in a worthwhile overall design process speedup at low cost and allowing algorithm upgrades with no hardware modification. The use of Fpgas as hardware accelerators is reviewed and then achievable speedups are predicted for logic simulation and VLSI design rule checking tasks for various Fpga co-processor arrangements.