Table of Contents
VLSI Design
Volume 4, Issue 3, Pages 167-179
http://dx.doi.org/10.1155/1996/25839

A Novel Path Delay Fault Simulator Using Binary Logic

1Department of ECE, Indian Institute of Science, Bangalore, India
2Microprocessor Applications Laboratory, Indian Institute of Science, Bangalore, India

Copyright © 1996 Hindawi Publishing Corporation. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

How to Cite this Article

Ananta K. Majhi, James Jacob, and Lalit M. Patnaik, “A Novel Path Delay Fault Simulator Using Binary Logic,” VLSI Design, vol. 4, no. 3, pp. 167-179, 1996. https://doi.org/10.1155/1996/25839.