Table of Contents
VLSI Design
Volume 4, Issue 1, Pages 83-90
http://dx.doi.org/10.1155/1996/51972

Design of an ASIC Chip for Skeletonization of Graylevel Digital Images

1Department of Electronics and Electrical Communication Engineering, Indian Institute of Technology, Kharagpur 721 302, India
2Department of Computer Science and Engineering, Indian Institute of Technology, Kharagpur 721 302, India

Received 1 December 1992; Revised 5 April 1993

Copyright © 1996 Hindawi Publishing Corporation. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Abstract

This paper describes the design of an ASIC chip for thinning of graylevel images. The chip implements a Min-Max skeletonization algorithm and is based on a pipeline architecture where each stage of the pipeline performs masking operations on the graylevel images. The chip operates in real time at a frequency of 8 MHz and utilizes about 321 mils × 410 mils of silicon area.