Design of an ASIC Chip for Skeletonization of Graylevel Digital Images
B. Majumdar,1V. V. Ramakrishna,2P. S. Dey,2and A. K. Majumdar2
Received01 Dec 1992
Revised05 Apr 1993
Abstract
This paper describes the design of an ASIC chip for thinning of graylevel images. The chip implements a Min-Max skeletonization algorithm and is based on a pipeline architecture where each stage of the pipeline performs masking operations on the graylevel images. The chip operates in real time at a frequency of 8 MHz and utilizes about 321 mils × 410 mils of silicon area.
