Table of Contents
VLSI Design
Volume 4, Issue 2, Pages 91-105
http://dx.doi.org/10.1155/1996/56545

An Evaluation of Parallel Synchronous and Conservative Asynchronous Logic-Level Simulations

1Computer Science and Engineering, University of Bridgeport, CT 06601, USA
2Washington State University at Tri-Cities, Richland, WA 99352, USA

Copyright © 1996 Hindawi Publishing Corporation. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

How to Cite this Article

Ausif Mahmood and William I. Baker, “An Evaluation of Parallel Synchronous and Conservative Asynchronous Logic-Level Simulations,” VLSI Design, vol. 4, no. 2, pp. 91-105, 1996. https://doi.org/10.1155/1996/56545.