Table of Contents Author Guidelines Submit a Manuscript
VLSI Design
Volume 5, Issue 1, Pages 37-48
http://dx.doi.org/10.1155/1996/58084

A Fast Clustering-Based Min-Cut Placement Algorithm With Simulated-Annealing Performance

Department of Computer Engineering and Computer Science, University of Missouri-Columbia, Columbia, MO 65211, USA

Received 6 September 1994; Accepted 30 January 1995

Copyright © 1996 Hindawi Publishing Corporation. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Abstract

Placement is an important constrained optimization problem in the design of very large scale (VLSI) integrated circuits [1–4]. Simulated annealing [5] and min-cut placement [6] are two of the most successful approaches to the placement problem. Min-cut methods yield less congested and more routable placements at the expense of more wire-length, while simulated annealing methods tend to optimize more the total wire-length with little emphasis on the minimization of congestion. It is also well known that min-cut algorithms are substantially faster than simulated-annealing-based methods. In this paper, a fast min-cut algorithm (ROW-PLACE) for row-based placement is presented and is empirically shown to achieve simulated-annealing-quality wire-length on a number of benchmark circuits. In comparison with Timberwolf 6 [7], ROW-PLACE is at least 12 times faster in its normal mode and is at least 25 times faster in its faster mode. The good results of ROW-PLACE are achieved using a very effective clustering-based partitioning algorithm in combination with constructive methods that reduce the wire-length of nets involved in terminal propagation.