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VLSI Design
Volume 4, Issue 2, Pages 119-133
http://dx.doi.org/10.1155/1996/60318

A Hardware Accelerator for Fault Simulation Utilizing a Reconfigurable Array Architecture

1Electrical Engineering Dept., Yonsei University, Seoul, Korea
2Dept. of Electrical and Computer Engineering, The University of Texas at Austin, Austin 78712, TX, USA

Copyright © 1996 Hindawi Publishing Corporation. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

How to Cite this Article

Sungho Kang, Youngmin Hur, and Stephen A. Szygenda, “A Hardware Accelerator for Fault Simulation Utilizing a Reconfigurable Array Architecture,” VLSI Design, vol. 4, no. 2, pp. 119-133, 1996. https://doi.org/10.1155/1996/60318.