Table of Contents
VLSI Design
Volume 4, Issue 1, Pages 1-10

A Multi-Terminal Net Router for Field-Programmable Gate Arrays

1Design Automation Laboratory, Department of Electrical & Computer Engineering and Computer Science, P.O. Box 210030, University of Cincinnati, Cincinnati 45221-0030, OH, USA
2Amit Chowdhary Department of Electrical Engineering and Computer Science, University of Michigan, 1301 Beal Avenue, Ann Arbor 48109-2122, MI, USA

Received 22 December 1993; Revised 18 October 1994

Copyright © 1996 Hindawi Publishing Corporation. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.


This paper presents a router for routing multi-terminal nets in field-programmable gate arrays (FPGAs). The router does not require pre-assignment of routing channels, a phase that is normally accomplished during global routing. This direct routing approach greatly enhances the probability of routing (routability). The multi-terminal routing greatly reduces the total wire length as it approximates a Steiner tree. The total number of segments required to route the circuits is usually less as compared to other routing approaches. The router has generated excellent routing results for some industrial circuits. The memory requirements for this router are very low. The time needed for the routing is linear with respect to the size of the circuit.