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VLSI Design
Volume 4, Issue 3, Pages 231-242
http://dx.doi.org/10.1155/1996/80472

Fault Modeling of ECL for High Fault Coverage of Physical Defects

1Dept. of Electrical & Computer Engineering, South Dakota School of Mines & Technology, Rapid City, SD 57701, USA
2Dept. of Computer Science, Colorado State University, Fort Collins, CO 80523, USA

Copyright © 1996 Hindawi Publishing Corporation. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Abstract

Bipolar Emitter Coupled Logic (ECL) devices can now be fabricated at higher densities and consumes much lower power. Behaviour of simple and complex ECL gates are examined in the presence of physical faults. The effectiveness of the classical stuck-at model in representing physical failures in ECL gates is examined. It is shown that the conventional stuck-at fault model cannot represent a majority of circuit level faults. A new augmented stuck-at fault model is presented which provides a significantly higher coverage of physical failures. The model may be applicable to other logic families that use logic gates with both true and complementary outputs. A design for testability approach is suggested for on-line detection of certain error conditions occurring in gates with true and complementary outputs which is a normal implementation for ECL devices.