Table of Contents Author Guidelines Submit a Manuscript
VLSI Design
Volume 4, Issue 3, Pages 257-269
http://dx.doi.org/10.1155/1996/84045

A Methodology for Testing Arbitrary Bilateral Bit-Level Systolic Arrays

1School of Computer Science, University of Windsor, Windsor, Ontario, N9B 3P4, Canada
2Department of Computer Science, University of South Carolina, Columbia 29208, SC, USA
3Electronics Unit, Indian Statistical Institute, Calcutta 700 035, India

Copyright © 1996 Hindawi Publishing Corporation. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

How to Cite this Article

S. Bandyopadhyay, A. Sengupta, and B. B. Bhattacharya, “A Methodology for Testing Arbitrary Bilateral Bit-Level Systolic Arrays,” VLSI Design, vol. 4, no. 3, pp. 257-269, 1996. https://doi.org/10.1155/1996/84045.