In this paper, we examine the effectiveness of combined logic and <mml:math xmlns:mml="http://www.w3.org/1998/Math/MathML"><mml:mrow><mml:msub><mml:mi>I</mml:mi><mml:mrow><mml:mi>D</mml:mi><mml:mi>D</mml:mi><mml:mi>Q</mml:mi></mml:mrow></mml:msub></mml:mrow></mml:math> testing to detectstuck-at and bridging faults. The stuck-at faults are detected by the logic test and <mml:math xmlns:mml="http://www.w3.org/1998/Math/MathML"><mml:mrow><mml:msub><mml:mi>I</mml:mi><mml:mrow><mml:mi>D</mml:mi><mml:mi>D</mml:mi><mml:mi>Q</mml:mi></mml:mrow></mml:msub></mml:mrow></mml:math>testing detects bridging faults.Near minimal stuck-at test sets are used for this combined logic and IDQQ test environment.These near minimal stuck-at test sets are generated using standard test programs, whileusing collapsed fault lists. We examined ISCAS &#39;85 and ISCAS &#39;89 benchmark circuitsunder this combined test environment. A comparison is given for the fault coverage obtainedunder this combined test environment with other studies based on pure logic test and <mml:math xmlns:mml="http://www.w3.org/1998/Math/MathML"><mml:mrow><mml:msub><mml:mi>I</mml:mi><mml:mrow><mml:mi>D</mml:mi><mml:mi>D</mml:mi><mml:mi>Q</mml:mi></mml:mrow></mml:msub></mml:mrow></mml:math>test. Also, the results of <mml:math xmlns:mml="http://www.w3.org/1998/Math/MathML"><mml:mrow><mml:msub><mml:mi>I</mml:mi><mml:mrow><mml:mi>D</mml:mi><mml:mi>D</mml:mi><mml:mi>Q</mml:mi></mml:mrow></mml:msub></mml:mrow></mml:math> based test sets (vectors generated specifically for <mml:math xmlns:mml="http://www.w3.org/1998/Math/MathML"><mml:mrow><mml:msub><mml:mi>I</mml:mi><mml:mrow><mml:mi>D</mml:mi><mml:mi>D</mml:mi><mml:mi>Q</mml:mi></mml:mrow></mml:msub></mml:mrow></mml:math> testing)are compared with that of stuck-at test sets. Finally, we present a case study on a microprogrammedprocessor using a functional test set to detect bridging faults in <mml:math xmlns:mml="http://www.w3.org/1998/Math/MathML"><mml:mrow><mml:msub><mml:mi>I</mml:mi><mml:mrow><mml:mi>D</mml:mi><mml:mi>D</mml:mi><mml:mi>Q</mml:mi></mml:mrow></mml:msub></mml:mrow></mml:math> testing.

S.  Hwang

R.  Rajsuman

VLSI Testing for High Reliability: Mixing <svg style="vertical-align:-4.88127pt" height="17.25" version="1.1" viewBox="0 0 36.424999 17.25" width="36.424999" xmlns:xlink="http://www.w3.org/1999/xlink" xmlns="http://www.w3.org/2000/svg"><g transform="matrix(.017,-0,0,-.017,.062,11.113)"><path id="x1D43C" d="M414 650l-6 -28q-63 -4 -78.5 -17.5t-27.5 -71.5l-77 -416q-11 -58 0.5 -71.5t77.5 -17.5l-5 -28h-275l8 28q63 4 79.5 18.5t27.5 70.5l80 416q11 57 -2 71t-81 18l6 28h273z" /></g><g transform="matrix(.012,-0,0,-.012,7.487,15.188)"><path id="x1D437" d="M780 372q0 -191 -178 -297q-128 -75 -335 -75h-250l7 27q61 7 77 22t28 76l77 398q11 62 0 76.5t-77 22.5l6 28h292q164 0 258.5 -67.5t94.5 -210.5zM678 375q0 119 -73 180.5t-201 61.5q-62 0 -82 -13q-17 -7 -25 -53l-80 -427q-8 -47 -4 -62t26 -20q24 -6 80 -6&#xA;q166 0 262.5 95t96.5 244z" /></g><g transform="matrix(.012,-0,0,-.012,17.042,15.188)"><use xlink:href="#x1D437"/></g><g transform="matrix(.012,-0,0,-.012,26.597,15.188)"><path id="x1D444" d="M745 361q0 -134 -83.5 -233t-214.5 -130l16 -11q97 -67 250 -132l-8 -23q-76 3 -131 16q-81 19 -242 125l-20 13q-129 8 -209 91t-80 208q0 160 116 271t289 111q136 0 226.5 -83t90.5 -223zM645 356q0 127 -57.5 201.5t-169.5 74.5q-126 0 -210.5 -104.5t-84.5 -248.5&#xA;q0 -97 46 -166.5t129 -87.5l84 15l29 -19q104 21 169 121.5t65 213.5z" /></g></svg> Testing
With Logic Testing

The effects of Built-In Current Sensors (BICS) on <mml:math id="E1" xmlns:mml="http://www.w3.org/1998/Math/MathML"><mml:mrow><mml:msub><mml:mi>I</mml:mi><mml:mrow><mml:mi>D</mml:mi><mml:mi>D</mml:mi><mml:mi>Q</mml:mi></mml:mrow></mml:msub></mml:mrow></mml:math>
 measurements as well as on the
performance of the circuit under test are considered. Most of the Built-In Current Sensor
designs transform the ground terminal of the circuit under test into a virtual ground. This
causes increases in both propagation delay and <mml:math id="E2" xmlns:mml="http://www.w3.org/1998/Math/MathML"><mml:mrow><mml:msub><mml:mi>I</mml:mi><mml:mrow><mml:mi>D</mml:mi><mml:mi>D</mml:mi><mml:mi>Q</mml:mi></mml:mrow></mml:msub></mml:mrow></mml:math>
 sampling time with the increase in the
number of gates, affecting both test as well as operational performance. The effects that
current sensors have on the operational and test performance of a circuit are considered.
Circuit partitioning may be used for overcoming the effects of BICS on <mml:math id="E3" xmlns:mml="http://www.w3.org/1998/Math/MathML"><mml:mrow><mml:msub><mml:mi>I</mml:mi><mml:mrow><mml:mi>D</mml:mi><mml:mi>D</mml:mi><mml:mi>Q</mml:mi></mml:mrow></mml:msub></mml:mrow></mml:math>
 measurements
as well as on the performance of the circuit under test.

Sankaran M. Menon

Yashwant K. Malaiya

Anura P. Jayasumana

Carol Q. Tong

Operational and Test Performance in the Presence of
Built-in Current Sensors

The behavior of basic CMOS combinational gates in the presence of a floating gate defect is
characterized in order to investigate its detectability by <mml:math id="E1" xmlns:mml="http://www.w3.org/1998/Math/MathML"><mml:mrow><mml:msub><mml:mi>I</mml:mi><mml:mrow><mml:mi>D</mml:mi><mml:mi>D</mml:mi><mml:mi>Q</mml:mi></mml:mrow></mml:msub></mml:mrow></mml:math>
. The defect is modeled at the
circuit level by the poly-bulk and metal-poly capacitances, which determine the quiescent
power supply current consumption (<mml:math id="E2" xmlns:mml="http://www.w3.org/1998/Math/MathML"><mml:mrow><mml:msub><mml:mi>I</mml:mi><mml:mrow><mml:mi>D</mml:mi><mml:mi>D</mml:mi><mml:mi>Q</mml:mi></mml:mrow></mml:msub></mml:mrow></mml:math>
) of the defective circuit. The testing implications
on the type of defective gate are studied. Experimental measures have been made on basic
CMOS combinational modules designed with intentional floating gate defects. A good agreement
is observed between the simulation results and the experimental data. A conventional
ATPG for stuck-at faults is used to obtain the required exciting vector to test the floating gate
defects by <mml:math id="E3" xmlns:mml="http://www.w3.org/1998/Math/MathML"><mml:mrow><mml:msub><mml:mi>I</mml:mi><mml:mrow><mml:mi>D</mml:mi><mml:mi>D</mml:mi><mml:mi>Q</mml:mi></mml:mrow></mml:msub></mml:mrow></mml:math>
 Testing.

Victor H. Champac

Joan Figueras

Current Testing of CMOS Combinational Circuits with
Single Floating Gate Defects

In this paper, we present two studies. The first study constitutes an assessment of the effectiveness
of IDDQ (quiescent power supply current) in detecting transistor-level defects for
three CMOS logic design styles. This study was carded out by designing, simulating, fabricating,
and testing CMOS devices with built-in defects. The second study involves an
assessment of IDDQ in a production-type environment and the effect of bum-in on IDDQ
levels. This study was carried out in a production facility. The results show that IDDQ testing
can detect some types of defects in precharge and pseudo-NMOS circuits but may require
partitioning circuitry for the latter.

A. Toukmaji

R. Helms

R. Makki

W. Mikhail

R. Toole

IDDQ Testing Experiments for Various CMOS Logic
Design Structures

Undetectable stuck-at faults in combinational circuits are related to the existence of logic
redundancy (s-redundancy). Similarly, logically equivalent nodes may cause some bridging
faults to become undetectable by <mml:math id="E1" xmlns:mml="http://www.w3.org/1998/Math/MathML"><mml:mrow><mml:msub><mml:mi>I</mml:mi><mml:mrow><mml:mi>D</mml:mi><mml:mi>D</mml:mi><mml:mi>Q</mml:mi></mml:mrow></mml:msub></mml:mrow></mml:math> testing. An efficient method for the identification and
removal of such functionally equivalent nodes (f-redundant nodes) in combinational circuits
is presented. OBDD graphs are used to identify the functional equivalence of candidate to
f-redundancy nodes. An f-redundancy removal algorithm based on circuit transformations to
improve bridging fault testability, is also proposed. The efficiency of the identification and
removal of f-redundancy has been evaluated on a set of benchmark circuits.

E. Isern

J. Figueras

IDDQ Detectable Bridges in Combinational CMOS Circuits

This paper applies the time-domain testing technique and compares the effectiveness of transient voltage and dynamic power supply current measurements in detecting faults in
CMOS mixed-signal circuits. The voltage and supply current (iDDT) measurements are analyzed by three methods to detect the presence of a fault, and to establish which measurement
achieves higher confidence in the detection. Catastrophic, soft and stuck-at single fault conditions were introduced to the circuit-under-test (CUT). The time-domain technique tests
a mixed-signal CUT in a unified fashion, thereby eliminating the need to partition the CUT into separate analogue and digital modules.

Mahmoud A. Al-Qutayri

Peter R. Shepherd

Application of Dynamic Supply Current Monitoring to Testing Mixed-Signal Circuits

Rafic Z. Makki

Advancements in Power Supply Current Testing

This paper presents the design methodology used in PSS1, a high level synthesis system
designed for computation dominated applications. It includes a behavior synthesizer and an
area optimizer. Based on a pre-defined architecture, the behavior synthesizer translates a
description into a number of designs with different delays and hardware costs. Based on a
two-level layout model, the area optimizer fine-tunes the physical design using the information
feedback from the layout tools. All the tools are linked by an X-window interface in
which users can traverse among different tools and interactively change the design parameters.
The output is linked to Lager system [7], a silicon assembler. The layout model allows
a designer to interactively merge/split modules, change the shape of modules, and define the
pin positions of modules. Experiments show that a considerable area improvement has been
achieved using this methodology.

Fur-Shing Tsai

Yu-Chin Hsu

Layout Modeling and Design Space Exploration in Pss1 System

Most datapath synthesis approaches use a simple area model to evaluate design area quality.However, using such a simplified model could mislead synthesis tasks into generating inferiordesigns. This paper presents an extensive experimental study to validate the correlationbetween the tradition area model, our proposed area model, and the actual layouts. Theresults show that traditional area quality measures are not good indicators for optimization indatapath synthesis. Moreover, this paper also shows that to provide accurate indications fordesign tradeoffs in high-level synthesis, the fidelity of the estimates is more important thanthe accuracy.

Allen C.-H. Wu

Datapath Optimization Using Layout Information: An Empirical Study

Submicron feature sizes result in designs in which power density is significantly increased.
High-level synthesis strategies are proposed in this paper to relieve potential thermal problems.
Operators are placed as close as possible to their data predecessors in order to minimize
the interconnection cost while not violating the thermal constraints. Spreading overused
functional units away from the thermal problem area often results in performance degradation.
Introducing redundant operators is suggested to reduce the module utilization and hence
thermal problems among problem modules when system performance is important. Our
experimental results show that this technique produces quite satisfactory results for a powerdominated
example.

Jen-Pin Weng

Alice C. Parker

Taking Thermal Considerations Into Account During
High-Level Synthesis

Accurate design descriptions during synthesis allow efficient use of resources. The appropriate
use of distinct implementations of RTL operators helps generate optimal VLSI designs.
The system presented here utilizes libraries composed of multiple modules with identical
functionality, but distinct performance and area characteristics. Such libraries allow the
generation of an accurate estimate of the area and delay of the final design during synthesis.
Full use of the module selection capability is possible by allowing the user to specify a total
area limit rather than a detailed allocation. Consequently, tradeoffs between different allocations
can be fully explored. Scheduling, module selection, and allocation are performed
simultaneously to achieve optimal use of area and delay, and to facilitate the incorporation of
lower level design considerations into behavioral synthesis. Synthesis decisions are made in
a time-constrained and area-constrained fashion, by using both constraints to identify and
avoid infeasible design possibilities. Module selection, scheduling, and allocation for pipelined
designs is also implemented. Experimental results show that the use of module selection
and time-and-area-constrained synthesis results in an area/delay design curve which is
superior to the results of traditional systems.

Ian G. Harris

Alex Orailoglu

Module Selection in Microarchitectural Synthesis for
Multiple Critical Constraint Satisfaction

The system-level design process typically involves refining a design specification down to
the point where each of the system's components is described as a block diagram or netlist
of abstract Register-Transfer (RT) level components. In this paper, we motivate the need for
such a standard RT component set, and describe a library environment that supports automatic
model generation, design reuse, and synthesis with technology-specific estimators. We
demonstrate the efficacy of the standard RT-component set approach with experiments performed
on the HLSW92 benchmarks. Our preliminary results indicate only a small overhead
of about 10% in using these standard, generic components. We then describe an automatic
model generation and technology projection scheme that uses fast (on-line) estimators for
predicting the area and delay of generic RT components tuned to a particular technology
library with an accuracy of 10%. These model generators and estimators have been integrated
with a high-level synthesis system at U.C. Irvine.

Nikil D. Dutt

Pradip K. Jha

RT Component Sets for High-Level Design Applications

The increasing complexity of VLSI design process has led to an increasing use of layout
synthesis systems. For many components of a high-level synthesis system such as module
generators and module generator development environments, an accurate model of area and
delay for the layouts generated by a layout synthesis system is extremely desirable. We have
experimented with a statistical model for area and delay of function modules. This model is
surprisingly accurate for a standard cell based layout synthesis systemૼVPNR. The area of
adder and shifter modules can be modeled to with in 5% accuracy while the error in delay
model is bounded by 4%. This model can be taken through another level of indirection
without significant loss in accuracy. The area of all the modules that fit a ripple-template
(such as carry-ripple adder) can be modeled with in 30% accuracy. The delay of these
modules has a better fit, 15%. The square-template designs (such as array multiplier) have an
area model with 1.7% coeificient of variance. In these cases, the model is parametrized by
the area and delay of the leaf cells in the template.

Akhilesh Tyagi

Statistical Module Level Area and Delay Estimation

Traditionally logic synthesis and layout tools optimize designs without interaction betweenthem. Lack of communication between the two tools often results in inferior post-layoutcircuit implementations. This paper presents three aspects of coupling synthesis with layoutto minimize post-layout area and delay of circuits. It presents two new techniques for computingnet-weights based on timing slacks, and shows how performance improvement withlittle overhead in area can be achieved. Secondly, it presents a novel idea of exploiting logicequivalence information in circuits to minimize circuit area and delay during layout. Analgorithm for computing logic equivalence classes and performing net swapping using theequivalence classes during layout is described. Lastly, it shows the sensitivity of post-layoutdelays of circuits to wiring models used in synthesis and demonstrates how resynthesistechniques can be effectively used to generate good post-layout implementation. Significantreductions in post-layout area and delay on several industrial designs have been observed.

Mandalagiri S. Chandrasekhar

Robert H. McCharles

David E. Wallace

Effective Coupling Between Logic Synthesis and LayoutTools for Synthesis of Area and Speed-Efficient Circuits

Due to the significant contribution of interconnect to the area and speed of today's circuits
and the technological trend toward smaller and faster gates which will make the effects of
interconnect even more substantial, interconnect optimization must be performed during all
phases of the design. The premise of this paper is that by increasing the interaction between
logic synthesis and physical design, circuits with smaller area and interconnection length,
and improved performance and routability can be obtained compared to when the two processes
are done separately. In particular, this paper describes an integrated approach to
technology mapping and physical design which finds solutions in both domains of design
representation simultaneously and interactively. The two processes are performed in lockstep:
technology mapping takes advantage of detailed information about the interconnect
delays and the layout cost of various optimization alternatives; placement itself is guided by
the evolving logic structure and accurate path-based delay traces. Using these techniques,
circuits with smaller area and higher performance have been synthesized.

Massoud Pedram

Narasimha Bhat

Ernest S. Kuh

Combining Technology Mapping With Layout

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