Abstract
Traditionally logic synthesis and layout tools optimize designs without interaction between them. Lack of communication between the two tools often results in inferior post-layout circuit implementations. This paper presents three aspects of coupling synthesis with layout to minimize post-layout area and delay of circuits. It presents two new techniques for computing net-weights based on timing slacks, and shows how performance improvement with little overhead in area can be achieved. Secondly, it presents a novel idea of exploiting logic equivalence information in circuits to minimize circuit area and delay during layout. An algorithm for computing logic equivalence classes and performing net swapping using the equivalence classes during layout is described. Lastly, it shows the sensitivity of post-layout delays of circuits to wiring models used in synthesis and demonstrates how resynthesis techniques can be effectively used to generate good post-layout implementation. Significant reductions in post-layout area and delay on several industrial designs have been observed.