Table of Contents
VLSI Design
Volume 5, Issue 2, Pages 111-124

Combining Technology Mapping With Layout

1Department of EE—Systems, University of Southern California, Los Angeles, CA 90089, USA
2Synopsys, 700 E. Middlefield Road, Mountain View, CA 94043, USA
3Department of EECS, University of California, Berkeley, CA 94720, USA

Copyright © 1997 Hindawi Publishing Corporation. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Citations to this Article [4 citations]

The following is the list of published articles that have cited the current article.

  • J. Cong, and D.Z. Pan, “Interconnect delay estimation models for synthesis and design planning,” pp. 97–100vol.1, . View at Publisher · View at Google Scholar
  • J Cong, and Z Pan, “Interconnect performance estimation models for design planning,” Ieee Transactions On Computer-Aided Design Of Integrated Circuits And Syste, vol. 20, no. 6, pp. 739–752, 2001. View at Publisher · View at Google Scholar
  • J Cong, “An interconnect-centric design flow for nanometer technologies,” Proceedings Of The Ieee, vol. 89, no. 4, pp. 505–528, 2001. View at Publisher · View at Google Scholar
  • Alastair M. Smith, George A. Constantinides, and Peter Y. K. Cheung, “Integrated Floorplanning, Module-Selection, and Architecture Generation for Reconfigurable Devices,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 16, no. 6, pp. 733–744, 2008. View at Publisher · View at Google Scholar