Table of Contents
VLSI Design
Volume 5, Issue 2, Pages 111-124

Combining Technology Mapping With Layout

1Department of EE—Systems, University of Southern California, Los Angeles, CA 90089, USA
2Synopsys, 700 E. Middlefield Road, Mountain View, CA 94043, USA
3Department of EECS, University of California, Berkeley, CA 94720, USA

Copyright © 1997 Hindawi Publishing Corporation. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

How to Cite this Article

Massoud Pedram, Narasimha Bhat, and Ernest S. Kuh, “Combining Technology Mapping With Layout,” VLSI Design, vol. 5, no. 2, pp. 111-124, 1997.