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VLSI Design
Volume 5, Issue 3, Pages 273-284
http://dx.doi.org/10.1155/1997/97381

Current Testing of CMOS Combinational Circuits with Single Floating Gate Defects

1lnstituto Nacional de Astrofísica, Optica y Electrónica, Grupo de Diseño de CI, Apdo. Postal 51 y 216, Puebla, Pue. 72000, Mexico
2Universitat Politècnica de Catalunya, Departament d'Enginyeria Electrónica, Diagonal 649, Planta 9, Barcelona 08028, Spain

Copyright © 1997 Hindawi Publishing Corporation. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

How to Cite this Article

Victor H. Champac and Joan Figueras, “Current Testing of CMOS Combinational Circuits with Single Floating Gate Defects,” VLSI Design, vol. 5, no. 3, pp. 273-284, 1997. https://doi.org/10.1155/1997/97381.